SNLS477B October 2014 – November 2018 DS90UB948-Q1
The D_GPIO[3:0] pins can be configured to obtain different sampling rates depending on the mode as well as back channel frequency. The mode is controlled by register 0x43 (Table 10). The back channel frequency can be controlled several ways:
The HSCC modes replace normal back-channel signaling with dedicated GPIOs or SPI data, allowing greater bandwidth for those functions. The HSCC Modes are enabled by setting the HSCC_MODE field in the HSCC_CONTROL register 0x43[2:0] in the DS90UB948-Q1. The HSCC modes eliminate the normal signaling such as Device ID, Capabilities, and RX Lock detect. It is intended to be turned on after obtaining RX Lock in normal back channel mode. Hence, the serializer properly determines capabilities prior to HSCC mode initiation. HSCC mode prevents loading capabilities, and it should only be enabled after RX Lock is established.
|HSCC_MODE (0x43[2:0])||MODE||NUMBER OF D_GPIOs||SAMPLES PER FRAME||D_GPIO EFFECTIVE FREQUENCY(1) (kHz)||D_GPIOs ALLOWED|
|5 Mbps BC(2)||10 Mbps BC(3)||20 Mbps BC(4)|