SNLS477B October 2014 – November 2018 DS90UB948-Q1
The DS90UB948-Q1 can be configured for several different operating modes via the MODE_SEL[1:0] input pins, or via the register bits 0x23 [4:2] (MODE_SEL1) and 0x49 (MODE_SEL0).
The DS90UB948-Q1 is capable of operating in either in 1-lane or 2-lane mode for FPD-Link III. By default, the FPD-Link III receiver automatically configures the input based on 1- or 2-lane mode operation. Programming register 0x34 [4:3] settings will override the automatic detection. For each FPD-Link III pair, the serial datastream is composed of a 35-bit symbol.
The DS90UB948-Q1 recovers the FPD-Link III serial datastream(s) and produces video data driven to the OpenLDI (LVDS) interface. OpenLDI single link and dual link are supported with color depths of 18 bits per pixel or 24 bits per pixel. There are 8 differential data pairs (D0 through D7) and two clock pairs (CLK1 and CLK2) on the OpenLDI interface. The number of data lines may vary, depending on the pixel formats supported. For single-link output the pixel clock is limited to 96 MHz. In the case of dual link, the pixel clock is limited to 192 MHz (or 96 MHz per LVDS port). When in a dual-link configuration, LVDS channels D0 to D3 carry ODD pixel data, and LVDS channels D4 to D7 carry EVEN pixel data.
The device can be configured in following modes: