SNLS477B October 2014 – November 2018 DS90UB948-Q1
GENERAL_CONFIGURATION_1 is described in Table 15.
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|6||BC_CRC_GENERATOR_ENABLE||R/W||0x1|| Back Channel CRC Generator Enable
|5||FAILSAFE_LOW||R/W||0x1|| Controls the pull direction for undriven LVCMOS inputs
1: Pull down
0: Pull up
|4||FILTER_ENABLE||R/W||0x1|| HS,VS,DE two clock filter
When enabled, pulses less than two full PCLK cycles on the DE, HS, and VS inputs will be rejected. For HS, It is a 2-clock filter for single FPD3 mode and a 4-clock filter for dual FPD3 mode.
1: Filtering enable
0: Filtering disable
|3||I2C_PASS_THROUGH||R/W||0x0|| I2C Pass-Through to Serializer if decode matches
0: Pass-Through Disabled
1: Pass-Through Enabled
|2||AUTO_ACK||R/W||0x0|| Automatically Acknowledge I2C writes independent of the forward channel lock state
|1||DE_GATE_RGB||R/W||0x0|| Gate RGB data with DE signal. RGB data is gated with DE in order to allow packetized audio and block unencrypted data when paired with a serializer that supports HDCP. When paired with a serializer that does not support HDCP, RGB data is not gated with DE by default. However, to enable packetized autio this bit must be set.
1: Gate RGB data with DE (has no effect when paired with a serializer that supports HDCP)
0: Pass RGB data independent of DE (has no effect when paired with a serializer that does not support HDCP)