SNLS477B October 2014 – November 2018 DS90UB948-Q1
HSCC_CONTROL is described in Table 63.
Return to Summary Table.
|4||SPI_MISO_MODE||R/W||0x0|| SPI MISO pin mode during Reverse SPI mode During Reverse SPI mode, SPI_MISO is typically an output signal. For bused SPI applications, it may be necessary to tri-state the SPI_MISO output if the device is not selected (SPI_SS = 0).
0 : Always enable SPI_MISO output driver
1 : Tri-state SPI_MISO output if SPI_SS is not asserted (low)
|3||SPI_CPOL||R/W||0x0|| SPI Clock Polarity Control
0 : SPI Data driven on Falling clock edge, sampled on Rising clock edge
1 : SPI Data driven on Rising clock edge, sampled on Falling clock edge
|2-0||HSCC_MODE||R/W||0x0|| High-Speed Control Channel Mode Enables high-speed modes for the secondary link back-channel, allowing higher speed signaling of GPIOs or SPI interface:
These bits indicates the High Speed Control Channel mode of operation:
000: Normal frame, GPIO mode
001: High Speed GPIO mode, 1 GPIO
010: High Speed GPIO mode, 2 GPIOs
011: High Speed GPIO mode: 4 GPIOs
110: High Speed, Forward Channel SPI mode
111: High Speed, Reverse Channel SPI mode