SNLS477B October 2014 – November 2018 DS90UB948-Q1
The Low-Speed Backward Channel provides bidirectional communication between the display and host processor. The information is carried from the deserializer to the serializer as serial frames. The back channel control data is transferred over both serial links along with the high-speed forward data, DC balance coding and embedded clock information. This architecture provides a backward path across the serial link together with a high-speed forward channel. The back channel contains the I2C, CRC and 4 bits of standard GPIO information with 5-Mbps or 20-Mbps line rate (configured by MODE_SEL1).