SNLS477B October 2014 – November 2018 DS90UB948-Q1
The DS90UB948-Q1 receives a 35-bit symbol over single or dual serial FPD-Link III pairs operating at up to 3.36 Gbps line rate in 1-lane FPD-Link III mode and 2.975 Gbps per lane in 2-lane FPD-Link III mode. The DS90UB948-Q1 converts this stream into a single or dual FPD-Link Interface (4 LVDS data channels + 1 LVDS clock, or 8 LVDS data channels + 2 LVDS clocks). The FPD-Link III serial stream contains an embedded clock, video control signals, and the DC-balanced video data and audio data which enhance signal quality to support AC coupling.
The DS90UB948-Q1 is intended for use with the DS90UB949-Q1 or DS90UB947-Q1 serializers, but is also backward compatible to the DS90UB925Q-Q1 and DS90UB927Q-Q1 FPD-Link III serializers.
The DS90UB948-Q1 deserializer attains lock to a data stream without the use of a separate reference clock source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the serializer regardless of the data pattern, delivering true automatic plug and lock performance. It can lock to the incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers the clock and data by extracting the embedded clock information, validating then deserializing the incoming data stream.
The DS90UB948-Q1 deserializer incorporates an I2C-compatible interface. The I2C-compatible interface allows programming of serializer or deserializer devices from a local host controller. The devices also incorporate a bidirectional control channel (BCC) that allows communication between serializer/deserializer as well as remote I2C slave devices.
The bidirectional control channel (BCC) is implemented through embedded signaling in the high-speed forward channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial link from one I2C bus to another. The implementation allows for arbitration with other I2C-compatible masters at either side of the serial link.