SNLS477B October   2014  – November 2018 DS90UB948-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1. 3.1 Typical Application
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  Timing Requirements for the Serial Control Bus
    8. 6.8  Switching Characteristics
    9. 6.9  Timing Diagrams and Test Circuits
    10. 6.10 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  FPD-Link III Port Register Access
      4. 7.3.4  Oscillator Output
      5. 7.3.5  Clock and Output Status
      6. 7.3.6  LVCMOS VDDIO Option
      7. 7.3.7  Power Down (PDB)
      8. 7.3.8  Interrupt Pin — Functional Description and Usage (INTB_IN)
      9. 7.3.9  General-Purpose I/O (GPIO)
        1. 7.3.9.1 GPIO[3:0] and D_GPIO[3:0] Configuration
        2. 7.3.9.2 Back Channel Configuration
        3. 7.3.9.3 GPIO Register Configuration
      10. 7.3.10 SPI Communication
        1. 7.3.10.1 SPI Mode Configuration
        2. 7.3.10.2 Forward Channel SPI Operation
        3. 7.3.10.3 Reverse Channel SPI Operation
      11. 7.3.11 Backward Compatibility
      12. 7.3.12 Adaptive Equalizer
        1. 7.3.12.1 Transmission Distance
        2. 7.3.12.2 Adaptive Equalizer Algorithm
        3. 7.3.12.3 AEQ Settings
          1. 7.3.12.3.1 AEQ Start-Up and Initialization
          2. 7.3.12.3.2 AEQ Range
          3. 7.3.12.3.3 AEQ Timing
      13. 7.3.13 I2S Audio Interface
        1. 7.3.13.1 I2S Transport Modes
        2. 7.3.13.2 I2S Repeater
        3. 7.3.13.3 I2S Jitter Cleaning
        4. 7.3.13.4 MCLK
      14. 7.3.14 Repeater
        1. 7.3.14.1 Repeater Configuration
        2. 7.3.14.2 Repeater Connections
          1. 7.3.14.2.1 Repeater Fan-Out Electrical Requirements
      15. 7.3.15 Built-In Self Test (BIST)
        1. 7.3.15.1 BIST Configuration and Status
          1. 7.3.15.1.1 Sample BIST Sequence
        2. 7.3.15.2 Forward Channel and Back Channel Error Checking
      16. 7.3.16 Internal Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Select MODE_SEL[1:0]
        1. 7.4.1.1 1-Lane FPD-Link III Input, Single Link OpenLDI Output
        2. 7.4.1.2 1-Lane FPD-Link III Input, Dual Link OpenLDI Output
        3. 7.4.1.3 2-Lane FPD-Link III Input, Dual Link OpenLDI Output
        4. 7.4.1.4 2-Lane FPD-Link III Input, Single Link OpenLDI Output
        5. 7.4.1.5 1-Lane FPD-Link III Input, Single Link OpenLDI Output (Replicate)
      2. 7.4.2 MODE_SEL[1:0]
      3. 7.4.3 OpenLDI Output Frame and Color Bit Mapping Select
    5. 7.5 Image Enhancement Features
      1. 7.5.1 White Balance
      2. 7.5.2 LUT Contents
      3. 7.5.3 Enabling White Balance
      4. 7.5.4 Adaptive Hi-FRC Dithering
    6. 7.6 Programming
      1. 7.6.1 Serial Control Bus
      2. 7.6.2 Multi-Master Arbitration Support
      3. 7.6.3 I2C Restrictions on Multi-Master Operation
      4. 7.6.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
      5. 7.6.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
      6. 7.6.6 Restrictions on Control Channel Direction for Multi-Master Operation
    7. 7.7 Register Maps
      1. 7.7.1 DS90UB948-Q1 Registers
        1. 7.7.1.1  I2C_DEVICE_ID Register (Address = 0x0) [reset = STRAP]
          1. Table 12. I2C_DEVICE_ID Register Field Descriptions
        2. 7.7.1.2  RESET Register (Address = 0x1) [reset = 0x0]
          1. Table 13. RESET Register Field Descriptions
        3. 7.7.1.3  GENERAL_CONFIGURATION_0 Register (Address = 0x2) [reset = 0x0]
          1. Table 14. GENERAL_CONFIGURATION_0 Register Field Descriptions
        4. 7.7.1.4  GENERAL_CONFIGURATION_1 Register (Address = 0x3) [reset = 0x70]
          1. Table 15. GENERAL_CONFIGURATION_1 Register Field Descriptions
        5. 7.7.1.5  BCC_WATCHDOG_CONTROL Register (Address = 0x4) [reset = 0xFE]
          1. Table 16. BCC_WATCHDOG_CONTROL Register Field Descriptions
        6. 7.7.1.6  I2C_CONTROL_1 Register (Address = 0x5) [reset = 0x1E]
          1. Table 17. I2C_CONTROL_1 Register Field Descriptions
        7. 7.7.1.7  I2C_CONTROL_2 Register (Address = 0x6) [reset = 0x0]
          1. Table 18. I2C_CONTROL_2 Register Field Descriptions
        8. 7.7.1.8  REMOTE_ID Register (Address = 0x7) [reset = 0x0]
          1. Table 19. REMOTE_ID Register Field Descriptions
        9. 7.7.1.9  SLAVEID_0 Register (Address = 0x8) [reset = 0x0]
          1. Table 20. SLAVEID_0 Register Field Descriptions
        10. 7.7.1.10 SLAVEID_1 Register (Address = 0x9) [reset = 0x0]
          1. Table 21. SLAVEID_1 Register Field Descriptions
        11. 7.7.1.11 SLAVEID_2 Register (Address = 0xA) [reset = 0x0]
          1. Table 22. SLAVEID_2 Register Field Descriptions
        12. 7.7.1.12 SLAVEID_3 Register (Address = 0xB) [reset = 0x0]
          1. Table 23. SLAVEID_3 Register Field Descriptions
        13. 7.7.1.13 SLAVEID_4 Register (Address = 0xC) [reset = 0x0]
          1. Table 24. SLAVEID_4 Register Field Descriptions
        14. 7.7.1.14 SLAVEID_5 Register (Address = 0xD) [reset = 0x0]
          1. Table 25. SLAVEID_5 Register Field Descriptions
        15. 7.7.1.15 SLAVEID_6 Register (Address = 0xE) [reset = 0x0]
          1. Table 26. SLAVEID_6 Register Field Descriptions
        16. 7.7.1.16 SLAVEID_7 Register (Address = 0xF) [reset = 0x0]
          1. Table 27. SLAVEID_7 Register Field Descriptions
        17. 7.7.1.17 SLAVEALIAS_0 Register (Address = 0x10) [reset = 0x0]
          1. Table 28. SLAVEALIAS_0 Register Field Descriptions
        18. 7.7.1.18 SLAVEALIAS_1 Register (Address = 0x11) [reset = 0x0]
          1. Table 29. SLAVEALIAS_1 Register Field Descriptions
        19. 7.7.1.19 SLAVEALIAS_2 Register (Address = 0x12) [reset = 0x0]
          1. Table 30. SLAVEALIAS_2 Register Field Descriptions
        20. 7.7.1.20 SLAVEALIAS_3 Register (Address = 0x13) [reset = 0x0]
          1. Table 31. SLAVEALIAS_3 Register Field Descriptions
        21. 7.7.1.21 SLAVEALIAS_4 Register (Address = 0x14) [reset = 0x0]
          1. Table 32. SLAVEALIAS_4 Register Field Descriptions
        22. 7.7.1.22 SLAVEALIAS_5 Register (Address = 0x15) [reset = 0x0]
          1. Table 33. SLAVEALIAS_5 Register Field Descriptions
        23. 7.7.1.23 SLAVEALIAS_6 Register (Address = 0x16) [reset = 0x0]
          1. Table 34. SLAVEALIAS_6 Register Field Descriptions
        24. 7.7.1.24 SLAVEALIAS_7 Register (Address = 0x17) [reset = 0x0]
          1. Table 35. SLAVEALIAS_7 Register Field Descriptions
        25. 7.7.1.25 MAILBOX_18 Register (Address = 0x18) [reset = 0x0]
          1. Table 36. MAILBOX_18 Register Field Descriptions
        26. 7.7.1.26 MAILBOX_19 Register (Address = 0x19) [reset = 0x1]
          1. Table 37. MAILBOX_19 Register Field Descriptions
        27. 7.7.1.27 GPIO_9__and_GLOBAL_GPIO_CONFIG Register (Address = 0x1A) [reset = 0x0]
          1. Table 38. GPIO_9__and_GLOBAL_GPIO_CONFIG Register Field Descriptions
        28. 7.7.1.28 FREQUENCY_COUNTER Register (Address = 0x1B) [reset = 0x0]
          1. Table 39. FREQUENCY_COUNTER Register Field Descriptions
        29. 7.7.1.29 GENERAL_STATUS Register (Address = 0x1C) [reset = 0x0]
          1. Table 40. GENERAL_STATUS Register Field Descriptions
        30. 7.7.1.30 GPIO0_CONFIG Register (Address = 0x1D) [reset = 0x3]
          1. Table 41. GPIO0_CONFIG Register Field Descriptions
        31. 7.7.1.31 GPIO1_2_CONFIG Register (Address = 0x1E) [reset = 0x3]
          1. Table 42. GPIO1_2_CONFIG Register Field Descriptions
        32. 7.7.1.32 GPIO3_CONFIG Register (Address = 0x1F) [reset = 0x2]
          1. Table 43. GPIO3_CONFIG Register Field Descriptions
        33. 7.7.1.33 GPIO5_6_CONFIG Register (Address = 0x20) [reset = 0x0]
          1. Table 44. GPIO5_6_CONFIG Register Field Descriptions
        34. 7.7.1.34 GPIO7_8_CONFIG Register (Address = 0x21) [reset = 0x0]
          1. Table 45. GPIO7_8_CONFIG Register Field Descriptions
        35. 7.7.1.35 DATAPATH_CONTROL Register (Address = 0x22) [reset = 0x0]
          1. Table 46. DATAPATH_CONTROL Register Field Descriptions
        36. 7.7.1.36 RX_MODE_STATUS Register (Address = 0x23) [reset = X]
          1. Table 47. RX_MODE_STATUS Register Field Descriptions
        37. 7.7.1.37 BIST_CONTROL Register (Address = 0x24) [reset = 0x8]
          1. Table 48. BIST_CONTROL Register Field Descriptions
        38. 7.7.1.38 BIST_ERROR_COUNT Register (Address = 0x25) [reset = 0x0]
          1. Table 49. BIST_ERROR_COUNT Register Field Descriptions
        39. 7.7.1.39 SCL_HIGH_TIME Register (Address = 0x26) [reset = 0x83]
          1. Table 50. SCL_HIGH_TIME Register Field Descriptions
        40. 7.7.1.40 SCL_LOW_TIME Register (Address = 0x27) [reset = 0x84]
          1. Table 51. SCL_LOW_TIME Register Field Descriptions
        41. 7.7.1.41 DATAPATH_CONTROL_2 Register (Address = 0x28) [reset = 0x20]
          1. Table 52. DATAPATH_CONTROL_2 Register Field Descriptions
        42. 7.7.1.42 FRC_CONTROL Register (Address = 0x29) [reset = 0x0]
          1. Table 53. FRC_CONTROL Register Field Descriptions
        43. 7.7.1.43 WHITE_BALANCE_CONTROL Register (Address = 0x2A) [reset = 0x0]
          1. Table 54. WHITE_BALANCE_CONTROL Register Field Descriptions
        44. 7.7.1.44 I2S_CONTROL Register (Address = 0x2B) [reset = 0x0]
          1. Table 55. I2S_CONTROL Register Field Descriptions
        45. 7.7.1.45 PCLK_TEST_MODE Register (Address = 0x2E) [reset = 0x0]
          1. Table 56. PCLK_TEST_MODE Register Field Descriptions
        46. 7.7.1.46 DUAL_RX_CTL Register (Address = 0x34) [reset = 0x1]
          1. Table 57. DUAL_RX_CTL Register Field Descriptions
        47. 7.7.1.47 AEQ_TEST Register (Address = 0x35) [reset = 0x0]
          1. Table 58. AEQ_TEST Register Field Descriptions
        48. 7.7.1.48 MODE_SEL Register (Address = 0x37) [reset = 0x0]
          1. Table 59. MODE_SEL Register Field Descriptions
        49. 7.7.1.49 I2S_DIVSEL Register (Address = 0x3A) [reset = 0x0]
          1. Table 60. I2S_DIVSEL Register Field Descriptions
        50. 7.7.1.50 EQ_STATUS Register (Address = 0x3B) [reset = 0x0]
          1. Table 61. EQ_STATUS Register Field Descriptions
        51. 7.7.1.51 LINK_ERROR_COUNT Register (Address = 0x41) [reset = 0x3]
          1. Table 62. LINK_ERROR_COUNT Register Field Descriptions
        52. 7.7.1.52 HSCC_CONTROL Register (Address = 0x43) [reset = 0x0]
          1. Table 63. HSCC_CONTROL Register Field Descriptions
        53. 7.7.1.53 ADAPTIVE_EQ_BYPASS Register (Address = 0x44) [reset = 0x60]
          1. Table 64. ADAPTIVE_EQ_BYPASS Register Field Descriptions
        54. 7.7.1.54 ADAPTIVE_EQ_MIN_MAX Register (Address = 0x45) [reset = 0x8]
          1. Table 65. ADAPTIVE_EQ_MIN_MAX Register Field Descriptions
        55. 7.7.1.55 FPD_TX_MODE Register (Address = 0x49) [reset = X]
          1. Table 66. FPD_TX_MODE Register Field Descriptions
        56. 7.7.1.56 LVDS_CONTROL Register (Address = 0x4B) [reset = 0x0]
          1. Table 67. LVDS_CONTROL Register Field Descriptions
        57. 7.7.1.57 CML_OUTPUT_CTL1 Register (Address = 0x52) [reset = 0x0]
          1. Table 68. CML_OUTPUT_CTL1 Register Field Descriptions
        58. 7.7.1.58 CML_OUTPUT_ENABLE Register (Address = 0x56) [reset = 0x0]
          1. Table 69. CML_OUTPUT_ENABLE Register Field Descriptions
        59. 7.7.1.59 CML_OUTPUT_CTL2 Register (Address = 0x57) [reset = 0x0]
          1. Table 70. CML_OUTPUT_CTL2 Register Field Descriptions
        60. 7.7.1.60 CML_OUTPUT_CTL3 Register (Address = 0x63) [reset = 0x0]
          1. Table 71. CML_OUTPUT_CTL3 Register Field Descriptions
        61. 7.7.1.61 PGCTL Register (Address = 0x64) [reset = 0x10]
          1. Table 72. PGCTL Register Field Descriptions
        62. 7.7.1.62 PGCFG Register (Address = 0x65) [reset = 0x0]
          1. Table 73. PGCFG Register Field Descriptions
        63. 7.7.1.63 PGIA Register (Address = 0x66) [reset = 0x0]
          1. Table 74. PGIA Register Field Descriptions
        64. 7.7.1.64 PGID Register (Address = 0x67) [reset = 0x0]
          1. Table 75. PGID Register Field Descriptions
        65. 7.7.1.65 PGDBG Register (Address = 0x68) [reset = 0x0]
          1. Table 76. PGDBG Register Field Descriptions
        66. 7.7.1.66 PGTSTDAT Register (Address = 0x69) [reset = 0x0]
          1. Table 77. PGTSTDAT Register Field Descriptions
        67. 7.7.1.67 GPI_PIN_STATUS_1 Register (Address = 0x6E) [reset = 0x0]
          1. Table 78. GPI_PIN_STATUS_1 Register Field Descriptions
        68. 7.7.1.68 GPI_PIN_STATUS_2 Register (Address = 0x6F) [reset = 0x0]
          1. Table 79. GPI_PIN_STATUS_2 Register Field Descriptions
        69. 7.7.1.69 RX_ID0 Register (Address = 0xF0) [reset = 0x5F]
          1. Table 80. RX_ID0 Register Field Descriptions
        70. 7.7.1.70 RX_ID1 Register (Address = 0xF1) [reset = 0x55]
          1. Table 81. RX_ID1 Register Field Descriptions
        71. 7.7.1.71 RX_ID2 Register (Address = 0xF2) [reset = 0x48]
          1. Table 82. RX_ID2 Register Field Descriptions
        72. 7.7.1.72 RX_ID3 Register (Address = 0xF3) [reset = 0x39]
          1. Table 83. RX_ID3 Register Field Descriptions
        73. 7.7.1.73 RX_ID4 Register (Address = 0xF4) [reset = 0x32]
          1. Table 84. RX_ID4 Register Field Descriptions
        74. 7.7.1.74 RX_ID5 Register (Address = 0xF5) [reset = 0x38]
          1. Table 85. RX_ID5 Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 FPD-Link III Interconnect Guidelines
        2. 8.2.2.2 AV Mute Prevention
        3. 8.2.2.3 Prevention of I2C Errors During Abrupt System Faults
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
    2. 9.2 Power Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Ground
    3. 10.3 Routing FPD-Link III Signal Traces
    4. 10.4 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

NKD Package
64-Pin WQFN
Top View
DS90UB948-Q1 UB948_Pin_Func_SNLS473.gif

Pin Functions

PIN I/O, TYPE DESCRIPTION
NAME NUMBER
OLDI OUTPUT PINS
CLK1–
CLK1+
37
36
O, LVDS Clock differential output pins
This pair requires an external 100-Ω termination for LVDS. Leave unused pins as No Connect. Do not connect to an external pullup or pulldown. Unused LVDS outputs, terminate with a single external 100-Ω termination at the end of the transmission line.
CLK2–
CLK2+
24
23
O, LVDS
D0–
D0+
43
42
O, LVDS Differential data output pins
This pair requires an external 100-Ω termination for LVDS. Leave unused pins as No Connect. Do not connect to an external pullup or pulldown. Unused LVDS outputs, terminate with a single external 100-Ω termination at the end of the transmission line.
D1–
D1+
41
40
O, LVDS
D2–
D2+
39
38
O, LVDS
D3–
D3+
35
34
O, LVDS
D4–
D4+
30
29
O, LVDS
D5–
D5+
28
27
O, LVDS
D6–
D6+
26
25
O, LVDS
D7–
D7+
22
21
O, LVDS
FPD-LINK III INTERFACE
RIN0– 54 I/O FPD-Link III RX Port 0 pins. The port receives FPD-Link III high-speed forward channel video and control data and transmits back channel control data. It can interface with a compatible FPD-Link III serializer TX through a STP or coaxial cable (see Figure 50 and Figure 51). It must be AC-coupled per Table 86. Leave unused pins as No Connect. Do not connect to an external pullup or pulldown.
RIN0+ 53 I/O
RIN1– 59 I/O FPD-Link III RX Port 1 pins. The port receives FPD-Link III high-speed forward channel video and control data and transmits back channel control data. It can interface with a compatible FPD-Link III serializer TX through a STP or coaxial cable (see Figure 50 and Figure 51). It must be AC-coupled per Table 86. Leave unused pins as No Connect. Do not connect to an external pullup or pulldown.
RIN1+ 58 I/O
CMF 55 I/O Common mode filter – connect 0.1-µF capacitor to GND
I2C PINS
I2C_SDA 46 I/O, OD I2C Data Input / Output Interface pin. See Serial Control Bus.
Open drain output; this pin must have an external pullup resistor to VI2CDO NOT FLOAT.
Recommend a 2.2 kΩ or 4.7 kΩ pullup to 1.8 V or 3.3 V respectively. See I2C Bus Pullup Resistor Calculation (SLVA689).
I2C_SCL 45 I/O, OD I2C Data Input / Output Interface pin. See Serial Control Bus.
Open drain output; this pin must have an external pullup resistor to VI2C DO NOT FLOAT.
Recommend a 2.2 kΩ or 4.7 kΩ pullup to 1.8 V or 3.3 V respectively. See I2C Bus Pullup Resistor Calculation (SLVA689).
IDx 47 I, S I2C Serial Control Bus Device ID Address Select configuration pin Connect to an external pullup to VDD18 and a pulldown to GND to create a voltage divider.
See Table 10.
SPI PINS
MOSI
(D_GPIO0)
19 I/O, PD SPI Master Output, Slave Input pin (function programmed through register)
It is a multifunction pin (shared with D_GPIO0) with a weak internal pulldown (3µA). Pin function is programmed through registers. If unused, tie to an external pulldown.
MISO
(D_GPIO1)
18 I/O, PD SPI Master Input, Slave Output pin (function programmed through register)
It is a multifunction pin (shared with D_GPIO1) with a weak internal pulldown (3µA). Pin function is programmed through registers. If unused, tie to an external pulldown.
SPLK
(D_GPIO2)
17 I/O, PD SPI Clock pin (function programmed through register)
It is a multifunction pin (shared with D_GPIO2) with a weak internal pulldown (3µA). Pin function is programmed through registers. If unused, tie to an external pulldown.
SS
(D_GPIO3)
16 I/O, PD SPI Slave Select pin (function programmed through register)
It is a multifunction pin (shared with D_GPIO0) with a weak internal pulldown (3µA). Pin function is programmed through registers. If unused, tie to an external pulldown.
CONTROL PINS
MODE_SEL0 61 I, S Mode Select 0 configuration pin
Connect to external pullup to VDD33 and pulldown to GND to create a voltage divider. See Configuration Select (MODE_SEL0) Table 8.
MODE_SEL1 50 I, S Mode Select 1 configuration pin
Connect to external pullup to VDD33 and pulldown to GND to create a voltage divider. See Configuration Select (MODE_SEL1) Table 9.
PDB 48 I, PD Inverted Power-Down input pin
Typically connected to a processor GPIO with a pulldown. When PDB input is brought HIGH, the device is enabled and internal registers and state machines are reset to default values. Asserting PDB signal low will power down the device and consume minimum power. The default function of this pin is PDB = LOW; POWER DOWN with an weak (>100-kΩ) internal pulldown enabled. PDB should remain low until after power supplies are applied and reach minimum required levels.
PDB = 1, device is enabled (normal operation)
PDB = 0, device is powered down
When the device is in the POWER DOWN state, the LVCMOS outputs are in tri-state, the PLL is shut down, and IDD is minimized.
BISTEN 5 I, PD BIST Enable pin
0: BIST mode is disabled
1: BIST mode is enabled
It is a configuration pin with a weak internal pulldown (3µA). If unused, tie to an external pulldown. See Built-In Self Test (BIST) for more information.
BISTC
(INTB_IN)
4 I, PD BIST Clock Select pin (function programmed through register)
0: PCLK
1: 33 MHz
It is a multifunction pin (shared with INTB_IN) with a weak internal pulldown (3µA). Pin function is programmed through registers. If unused, tie to an external pulldown.
INTB_IN
(BISTC)
4 I, PD Interrupt Input pin (default function).
It is a multifunction pin (shared with BISTC) with a weak internal pulldown (3µA). Pin function is programmed through registers. If unused, tie to an external pulldown. The INTB_IN pin may act as an output driver and pull low when PDB is low (see Interrupt Pin — Functional Description and Usage (INTB_IN)).
GPIO PINS
GPIO0
(SDOUT)
7 I/O General Purpose Input / Output 0 pin (default function)
default state: logic LOW
It is a multifunction pin (shared with SDOUT) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See General-Purpose I/O (GPIO). If unused, tie to an external pulldown.
GPIO1
(SWC)
8 I/O General Purpose Input / Output 1 pin (default function)
default state: logic LOW
It is a multifunction pin (shared with SWC) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See General-Purpose I/O (GPIO). If unused, tie to an external pulldown.
GPIO2
(I2S_DC)
10 I/O General Purpose Input / Output 2 pin (default function)
default state: logic LOW
It is a multifunction pin (shared with I2S_DC) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See General-Purpose I/O (GPIO). If unused, tie to an external pulldown.
GPIO3
(I2S_DD)
9 I/O General Purpose Input / Output 3 pin (default function)
default state: logic LOW
It is a multifunction pin (shared with I2C_DD) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See General-Purpose I/O (GPIO). If unused, tie to an external pulldown.
GPIO9
(MCLK)
15 I/O General Purpose Input / Output 9 pin (default function)
default state: logic LOW
It is a multifunction pin (shared with MCLK) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See General-Purpose I/O (GPIO). If unused, tie to an external pulldown.
HIGH-SPEED GPIO PINS
D_GPIO0
(MOSI)
19 I/O High-Speed General Purpose Input / Output 0 pin (default function)
default state: tri-state
Only available in Dual Link Mode. It is a multifunction pin (shared with MOSI) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See General-Purpose I/O (GPIO). If unused, tie to an external pulldown.
D_GPIO1
(MISO)
18 I/O High-Speed General Purpose Input / Output 1 pin (default function)
default state: tri-state
Only available in Dual Link Mode. It is a multifunction pin (shared with MISO) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See General-Purpose I/O (GPIO). If unused, tie to an external pulldown.
D_GPIO2
(SPLK)
17 I/O High-Speed General Purpose Input / Output 2 pin (default function)
default state: tri-state
Only available in Dual Link Mode. It is a multifunction pin (shared with SPLK) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See General-Purpose I/O (GPIO). If unused, tie to an external pulldown.
D_GPIO3
(SS)
16 I/O High-Speed General Purpose Input / Output 3 pin (default function)
default state: tri-state
Only available in Dual Link Mode. It is a multifunction pin (shared with SS) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See General-Purpose I/O (GPIO). If unused, tie to an external pulldown.
REGISTER ONLY GPIO PINS
GPIO5_REG
(I2S_DB)
11 I/O High-Speed General Purpose Input / Output 5 pin (default function)
I2C register control only
default state: logic LOW
It is a multifunction pin (shared with I2S_DB) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See General-Purpose I/O (GPIO). If unused, tie to an external pulldown.
GPIO6_REG
(I2S_DA)
12 I/O High-Speed General Purpose Input / Output 6 pin (default function)
I2C register control only
default state: logic LOW
It is a multifunction pin (shared with I2S_DA) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See General-Purpose I/O (GPIO). If unused, tie to an external pulldown.
GPIO7_REG
(I2S_WC)
14 I/O High-Speed General Purpose Input / Output 7 pin (default function)
I2C register control only
default state: logic LOW
It is a multifunction pin (shared with I2S_WC) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See General-Purpose I/O (GPIO). If unused, tie to an external pulldown.
GPIO8_REG
(I2S_CLK)
13 I/O High-Speed General Purpose Input / Output 8 pin (default function)
I2C register control only
default state: logic LOW
It is a multifunction pin (shared with I2S_CLK) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See General-Purpose I/O (GPIO). If unused, tie to an external pulldown.
SLAVE MODE LOCAL I2S CHANNEL PINS
I2S_WC
(GPIO7_REG)
14 O Slave Mode I2S Word Clock Output pin (function programmed through register)
It is a multifunction pin (shared with GPIO7_REG). Pin function is programmed through registers. See I2S Audio Interface. If unused, tie to an external pulldown.
I2S_CLK
(GPIO8_REG)
13 O Slave Mode I2S Clock Output pin (function programmed through register)
NOTE: Disable I2S data jitter cleaner, when using these pins, through the register bit I2S Control: 0x2B[7]=1
It is a multifunction pin (shared with GPIO8_REG). Pin function is programmed through registers. See I2S Audio Interface. If unused, tie to an external pulldown.
I2S_DA
(GPIO6_REG)
12 O Slave Mode I2S Data Output pin (function programmed through register)
It is a multifunction pin (shared with GPIO6_REG). Pin function is programmed through registers. See I2S Audio Interface. If unused, tie to an external pulldown.
I2S_DB
(GPIO5_REG)
11 O Slave Mode I2S Data Output pin (function programmed through register)
It is a multifunction pin (shared with GPIO5_REG). Pin function is programmed through registers. See I2S Audio Interface. If unused, tie to an external pulldown.
I2S_DC
(GPIO2)
10 O Slave Mode I2S Data Output (function programmed through register)
It is a multifunction pin (shared with GPIO2). Pin function is programmed through registers. See I2S Audio Interface. If unused, tie to an external pulldown.
I2S_DD
(GPIO3)
9 O Slave Mode I2S Data Output (function programmed through register)
It is a multifunction pin (shared with GPIO3). Pin function is programmed through registers. See I2S Audio Interface. If unused, tie to an external pulldown.
MASTER MODE LOCAL I2S CHANNEL PINS
SWC
(GPIO1)
8 O Master Mode I2S Word Clock Output pin (function is programmed through registers)
(Pin is shared with GPIO1)
It is a multifunction pin (shared with GPIO1). Pin function is programmed through registers. See I2S Audio Interface. If unused, tie to an external pulldown.
SDOUT
(GPIO0)
7 O Master Mode I2S Data Output pin (function is programmed through registers)
(Pin is shared with GPIO0)
It is a multifunction pin (shared with GPIO0). Pin function is programmed through registers. See I2S Audio Interface. If unused, tie to an external pulldown.
MCLK
(GPIO9)
15 O Master Mode I2S System Clock Output pin (function is programmed through registers)
(Pin is shared with GPIO9)
It is a multifunction pin (shared with GPIO9). Pin function is programmed through registers. See I2S Audio Interface. If unused, tie to an external pulldown.
STATUS PINS
LOCK 1 O Lock Status Output pin
LOCK = 1: PLL acquired lock to the reference clock input
LOCK = 0: PLL is unlocked
PASS 7 O Normal mode status output pin (BISTEN = 0)
PASS = 1: No fault detected on input display timing
PASS = 0: Indicates an error condition or corruption in display timing. Fault condition occurs:
  1. DE length value mismatch measured once in succession
  2. VSync length value mismatch measured twice in succession
BIST mode status output pin (BISTEN = 1)
PASS = 1: No error detected
PASS = 0: Error detected
POWER and GROUND
VDD33_A,
VDD33_B
56
31
P 3.3-V (±10%) supply. Power to on-chip regulator. Requires 10-µF, 1-µF, 0.1-µF, and 0.01-µF capacitors to GND.
VDDIO 3 P LVCMOS I/O power supply: 1.8 V (±5%) OR 3.3 V (±10%). Requires 10-µF, 1-µF, 0.1-µF, and 0.01-µF capacitors to GND.
VDD12_LVDS
VDDP12_LVDS
VDDL12_0
VDDL12_1
VDDP12_CH0
VDDR12_CH0
VDDP12_CH1
VDDR12_CH1
20
32
6
44
51
52
60
57
P 1.2-V (±5%) supply. Requires 10-µF, 1-µF, 0.1-µF, and 0.01-µF capacitors to GND at each VDD pin.
CAP_I2S
VDD25_CAP
2
33
D Decoupling capacitor connection for on-chip regulator. Recommend to connect with a 0.1-μF decoupling capacitor to GND.
VSS DAP G DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 32 vias.
OTHER PINS
CMLOUTP
CMLOUTN
62
63
O Channel Monitor Loop-through Driver differential output pins Route to a test point or a pad with 100-Ω termination resistor between pins for channel monitoring (recommended). See Figure 47 or Figure 48.
RES0
RES1
49
64
- Reserved pins. 0.1-µF decoupling capacitor could be placed to GND. May be left floating as No Connect pins.
The following definitions define the functionality of the I/O cells for each pin.

I/O TYPE:
  • P = Power supply
  • G = Ground
  • D = Decoupling for an internal linear regulator
  • S = Configuration/Strap Input (All strap pins have internal pulldowns determined by IOZ specification. If the default strap value is needed to be changed then an external resistor should be used.
  • I = Input
  • O = Output
  • I/O = Input/Output
  • PD = Internal pulldown