SNLS477B October 2014 – November 2018 DS90UB948-Q1
When power is applied, power from the highest voltage rail to the lowest voltage rail on any of the supply pins. For 3.3-V IO operation, VDDIO and VDD33 can be powered by the same supply and ramped simultaneously. Use a large capacitor on the PDB pin to ensure PDB arrives after all the supply pins have settled to the recommended operating voltage. When PDB pin is pulled up to VDD33, a 10-kΩ pullup and a > 10–μF capacitor to GND are required to delay the PDB input signal rise. All inputs must not be driven until both VDD33 and VDDIO has reached steady state. Pins VDD33_A and VDD33_B must both be externally connected, bypassed, and driven to the same potential (they are not internally connected).