SNLS477B October 2014 – November 2018 DS90UB948-Q1
The device may also be configured by the use of a I2C-compatible serial control bus. Multiple devices may share the serial control bus (up to eight device addresses supported). The device address is set through a resistor divider (RHIGH and RLOW — see Figure 43 below) connected to the IDx pin.
The serial control bus consists of two signals, SCL and SDA. SCL is a serial bus clock input. SDA is the serial bus data input / output signal. Both SCL and SDA signals require an external pullup resistor to 1.8-V or 3.3-V VI2C. For most applications, TI recommends that the user adds a 4.7-kΩ pullup resistor to the VDD33 or 2.2 kΩ resistor to the VDD18. However, the pullup resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled high or driven low. For more details information on how to calculate the pullup resistor, see I2C Bus Pullup Resistor Calculation (SLVA689).
The IDx pin configures the control interface to one of eight possible device addresses. A pullup resistor and a pulldown resistor may be used to set the appropriate voltage ratio between the IDx input pin (VLOW) and VDD33, each ratio corresponding to a specific device address. See Table 10 for more information.
|SUGGESTED STRAP RESISTORS
|PRIMARY ASSIGNED I2C ADDRESS|
|V (TYP)||VDD = 3.3 V||R1 (kΩ)||R2 (kΩ)||7-BIT||8-BIT|
|1||0.169 x V(VDD33)||0.559||73.2||15||0x2E||0x5C|
|2||0.230 x V(VDD33)||0.757||66.5||20||0x30||0x60|
|3||0.295 x V(VDD33)||0.974||59||24.9||0x32||0x64|
|4||0.376 x V(VDD33)||1.241||49.9||30.1||0x34||0x68|
|5||0.466 x V(VDD33)||1.538||46.4||40.2||0x36||0x6C|
|6||0.556 x V(VDD33)||1.835||40.2||49.9||0x38||0x70|
|7||0.801 x V(VDD33)||2.642||18.7||75||0x3C||0x78|
The serial bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SDA transitions low while SCL is high. A STOP occurs when SCL transitions high while SDA is also HIGH. See Figure 44.
To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it acknowledges (ACKs) the master by driving the SDA bus low. If the address does not match the slave address of a device, the slave not-acknowledges (NACKs) the master by letting the SDA be pulled High. ACKs also occur on the bus when data is transmitted. When the master writes data, the slave sends an ACK after every data byte is successfully received. When the master reads data, the master sends an ACK after every data byte is received to let the slave know that the master is ready to receive another data byte. When the master wants to stop reading, the master sends a NACK after the last data byte to create a stop condition on the bus. All communication on the bus begins with either a start condition or a repeated Start condition. All communication on the bus ends with a stop condition. A READ is shown in Figure 45 and a WRITE is shown in Figure 46.
The I2C master located in the deserializer must support I2C clock stretching. For more information on I2C interface requirements and throughput considerations, refer to the I2C Communication Over FPD-Link III with Bidirectional Control Channel (SNLA131).