SLLSF22G April   2018  – June 2020 ISO1410 , ISO1412 , ISO1430 , ISO1432 , ISO1450 , ISO1452

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Application Schematic
  4. 4 Revision History
  5. 5 Description Continued
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
    1.     Pin Functions: Full-Duplex Device
    2.     Pin Functions: Half-Duplex Device
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Power Ratings
    6. 8.6  Insulation Specifications
    7. 8.7  Safety-Related Certifications
    8. 8.8  Safety Limiting Values
    9. 8.9  Electrical Characteristics: Driver
    10. 8.10 Electrical Characteristics: Receiver
    11. 8.11 Supply Current Characteristics: Side 1 (ICC1)
    12. 8.12 Supply Current Characteristics: Side 2 (ICC2)
    13. 8.13 Switching Characteristics: Driver
    14. 8.14 Switching Characteristics: Receiver
    15. 8.15 Insulation Characteristics Curves
    16. 8.16 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Electromagnetic Compatibility (EMC) Considerations
      2. 10.3.2 Failsafe Receiver
      3. 10.3.3 Thermal Shutdown
      4. 10.3.4 Glitch-Free Power Up and Power Down
    4. 10.4 Device Functional Modes
      1. 10.4.1 Device I/O Schematics
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Data Rate and Bus Length
        2. 11.2.2.2 Stub Length
        3. 11.2.2.3 Bus Loading
      3. 11.2.3 Application Curves
        1. 11.2.3.1 Insulation Lifetime
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 PCB Material
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Related Links
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 Community Resource
    5. 14.5 Trademarks
    6. 14.6 Electrostatic Discharge Caution
    7. 14.7 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

DW Package
16-Pin SOIC
Full-Duplex Device Top View
ISO1450 ISO1452 ISO1410 ISO1412 ISO1430 ISO1432 iso14xx-16-pin-sop-full-duplex-pinout.gif

Pin Functions: Full-Duplex Device

PIN I/O DESCRIPTION
NAME NO.
A 14 I Receiver non-inverting input on the bus side
B 13 I Receiver inverting input on the bus side
D 6 I Driver input
DE 5 I Driver enable. This pin enables the driver output when high and disables the driver output when low or open.
GND1(1) 2 — Ground connection for VCC1
GND1(1) 8 — Ground connection for VCC1
GND2(1) 9 — Ground connection for VCC2
GND2(1) 15 — Ground connection for VCC2
NC(2) 7 — No internal connection
NC(2) 10 — No internal connection
R 3 O Receiver output
RE 4 I Receiver enable. This pin disables the receiver output when high or open and enables the receiver output when low.
VCC1 1 — Logic-side power supply
VCC2 16 — Transceiver-side power supply
Y 11 O Driver non-inverting output
Z 12 O Driver inverting output
(1) For Logic side, both Pin 2 and Pin 8 must be connected to GND1. For Bus side, both Pin 9 and Pin 15 must be connected to GND2.
(2) Device functionality is not affected if NC pins are connected to supply or ground on PCB
DW Package
16-Pin SOIC
Half-Duplex Device Top View
ISO1450 ISO1452 ISO1410 ISO1412 ISO1430 ISO1432 iso14xx-16-pin-sop-half-duplex-pinout.gif

Pin Functions: Half-Duplex Device

PIN I/O DESCRIPTION
NAME NO.
A 12 I/O Transceiver non-inverting input or output (I/O) on the bus side
B 13 I/O Transceiver inverting input or output (I/O) on the bus side
D 6 I Driver input
DE 5 I Driver enable. This pin enables the driver output when high and disables the driver output when low or open.
GND1(1) 2 — Ground connection for VCC1
GND1(1) 8 — Ground connection for VCC1
GND2(1) 9 — Ground connection for VCC2
GND2(1) 15 — Ground connection for VCC2
NC(2) 7 — No internal connection
NC(2) 10 — No internal connection
NC(2) 11 — No internal connection
NC(2) 14 — No internal connection
R 3 O Receiver output
RE 4 I Receiver enable. This pin disables the receiver output when high or open and enables the receiver output when low.
VCC1 1 — Logic-side power supply
VCC2 16 — Transceiver-side power supply
(1) For Logic side, both Pin 2 and Pin 8 must be connected to GND1. For Bus side, both Pin 9 and Pin 15 must be connected to GND2.
(2) Device functionality is not affected if NC pins are connected to supply or ground on PCB