SWRS219B October 2018 – September 2019 IWR6843
ADVANCE INFORMATION for pre-production products; subject to change without notice.
Refer to the PDF data sheet for device specific package drawings
The supported IWR6843 LVDS lane configuration is two Data lanes (LVDS_TXP/M), one Bit Clock lane (LVDS_CLKP/M) and one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface is used for debugging. The LVDS interface supports the following data rates: