SWRS219B October   2018  – September 2019 IWR6843

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
      1. Table 4-3 PAD IO Register Bit Descriptions
    3. 4.3 Signal Descriptions
      1. Table 4-4 Signal Descriptions - Digital
      2. Table 4-5 Signal Descriptions - Analog
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Supply Specifications
    6. 5.6  Power Consumption Summary
    7. 5.7  RF Specification
    8. 5.8  CPU Specifications
    9. 5.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 5.10 Timing and Switching Characteristics
      1. 5.10.1  Power Supply Sequencing and Reset Timing
      2. 5.10.2  Input Clocks and Oscillators
        1. 5.10.2.1 Clock Specifications
      3. 5.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.10.3.1 Peripheral Description
        2. 5.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. Table 5-6 SPI Timing Conditions
          2. Table 5-7 SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. Table 5-8 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 5.10.3.3 SPI Slave Mode I/O Timings
          1. Table 5-9 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 5.10.3.4 Typical Interface Protocol Diagram (Slave Mode)
      4. 5.10.4  LVDS Interface Configuration
        1. 5.10.4.1 LVDS Interface Timings
      5. 5.10.5  General-Purpose Input/Output
        1. Table 5-11 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 5.10.6  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. Table 5-12 Dynamic Characteristics for the CANx TX and RX Pins
      7. 5.10.7  Serial Communication Interface (SCI)
        1. Table 5-13 SCI Timing Requirements
      8. 5.10.8  Inter-Integrated Circuit Interface (I2C)
        1. Table 5-14 I2C Timing Requirements
      9. 5.10.9  Quad Serial Peripheral Interface (QSPI)
        1. Table 5-15 QSPI Timing Conditions
        2. Table 5-16 Timing Requirements for QSPI Input (Read) Timings
        3. Table 5-17 QSPI Switching Characteristics
      10. 5.10.10 ETM Trace Interface
        1. Table 5-18 ETMTRACE Timing Conditions
        2. Table 5-19 ETM TRACE Switching Characteristics
      11. 5.10.11 Data Modification Module (DMM)
        1. Table 5-20 DMM Timing Requirements
      12. 5.10.12 JTAG Interface
        1. Table 5-21 JTAG Timing Conditions
        2. Table 5-22 Timing Requirements for IEEE 1149.1 JTAG
        3. Table 5-23 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Subsystems
      1. 6.3.1 RF and Analog Subsystem
        1. 6.3.1.1 Clock Subsystem
        2. 6.3.1.2 Transmit Subsystem
        3. 6.3.1.3 Receive Subsystem
      2. 6.3.2 Processor Subsystem
      3. 6.3.3 Host Interface
      4. 6.3.4 Master Subsystem Cortex-R4F
      5. 6.3.5 DSP Subsystem
      6. 6.3.6 Hardware Accelerator
    4. 6.4 Other Subsystems
      1. 6.4.1 ADC Channels (Service) for User Application
        1. Table 6-1 GP-ADC Parameter
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Reference Schematic
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
      3. 7.3.3 Stackup Details
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
  • ALA|209
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power Consumption Summary

Table 5-2 and Table 5-3 summarize the power consumption at the power terminals.

Table 5-2 Maximum Current Ratings at Power Terminals

PARAMETER SUPPLY NAME DESCRIPTION MIN TYP MAX UNIT
Current consumption VDDIN, VIN_SRAM, VNWA Total current drawn by all nodes driven by 1.2V rail 1000 mA
VIN_13RF1, VIN_13RF2 Total current drawn by all nodes driven by 1.3V rail 2000
VIOIN_18, VIN_18CLK, VIOIN_18DIFF, VIN_18BB, VIN_18VCO Total current drawn by all nodes driven by 1.8V rail 850
VIOIN Total current drawn by all nodes driven by 3.3V rail 50

Table 5-3 Average Power Consumption at Power Terminals

PARAMETER CONDITION DESCRIPTION MIN TYP MAX UNIT
Average power consumption 1.0-V internal LDO bypass mode 25% Duty Cycle 1TX, 4RX Use Case: Low power mode, 3.2 MSps complex transceiver, 25-ms frame time, 128 chirps, 128 samples/chirp, 8-µs interchirp time (25% duty cycle), DSP active TBD W
2TX, 4RX(1) TBD
50% Duty Cycle 1TX, 4RX Use Case: Low power mode, 3.2 MSps complex transceiver, 25-ms frame time, 256 chirps, 128 samples/chirp, 8-µs interchirp time (50% duty cycle), DSP active TBD
2TX, 4RX(1) TBD
1.3-V internal LDO enabled mode 25% Duty Cycle 1TX, 4RX Use Case: Low power mode, 3.2 MSps complex transceiver, 25-ms frame time, 128 chirps, 128 samples/chirp, 8-µs interchirp time (25% duty cycle), DSP active TBD
2TX, 4RX(1) TBD
50% Duty Cycle 1TX, 4RX Use Case: Low power mode, 3.2 MSps complex transceiver, 25-ms frame time, 256 chirps, 128 samples/chirp, 8-µs interchirp time (50% duty cycle), DSP active TBD
2TX, 4RX(1) TBD
Two TX antennas are on simultaneously.