SWRS219B October   2018  – September 2019 IWR6843

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
      1. Table 4-3 PAD IO Register Bit Descriptions
    3. 4.3 Signal Descriptions
      1. Table 4-4 Signal Descriptions - Digital
      2. Table 4-5 Signal Descriptions - Analog
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Supply Specifications
    6. 5.6  Power Consumption Summary
    7. 5.7  RF Specification
    8. 5.8  CPU Specifications
    9. 5.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 5.10 Timing and Switching Characteristics
      1. 5.10.1  Power Supply Sequencing and Reset Timing
      2. 5.10.2  Input Clocks and Oscillators
        1. 5.10.2.1 Clock Specifications
      3. 5.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.10.3.1 Peripheral Description
        2. 5.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. Table 5-6 SPI Timing Conditions
          2. Table 5-7 SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. Table 5-8 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 5.10.3.3 SPI Slave Mode I/O Timings
          1. Table 5-9 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 5.10.3.4 Typical Interface Protocol Diagram (Slave Mode)
      4. 5.10.4  LVDS Interface Configuration
        1. 5.10.4.1 LVDS Interface Timings
      5. 5.10.5  General-Purpose Input/Output
        1. Table 5-11 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 5.10.6  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. Table 5-12 Dynamic Characteristics for the CANx TX and RX Pins
      7. 5.10.7  Serial Communication Interface (SCI)
        1. Table 5-13 SCI Timing Requirements
      8. 5.10.8  Inter-Integrated Circuit Interface (I2C)
        1. Table 5-14 I2C Timing Requirements
      9. 5.10.9  Quad Serial Peripheral Interface (QSPI)
        1. Table 5-15 QSPI Timing Conditions
        2. Table 5-16 Timing Requirements for QSPI Input (Read) Timings
        3. Table 5-17 QSPI Switching Characteristics
      10. 5.10.10 ETM Trace Interface
        1. Table 5-18 ETMTRACE Timing Conditions
        2. Table 5-19 ETM TRACE Switching Characteristics
      11. 5.10.11 Data Modification Module (DMM)
        1. Table 5-20 DMM Timing Requirements
      12. 5.10.12 JTAG Interface
        1. Table 5-21 JTAG Timing Conditions
        2. Table 5-22 Timing Requirements for IEEE 1149.1 JTAG
        3. Table 5-23 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Subsystems
      1. 6.3.1 RF and Analog Subsystem
        1. 6.3.1.1 Clock Subsystem
        2. 6.3.1.2 Transmit Subsystem
        3. 6.3.1.3 Receive Subsystem
      2. 6.3.2 Processor Subsystem
      3. 6.3.3 Host Interface
      4. 6.3.4 Master Subsystem Cortex-R4F
      5. 6.3.5 DSP Subsystem
      6. 6.3.6 Hardware Accelerator
    4. 6.4 Other Subsystems
      1. 6.4.1 ADC Channels (Service) for User Application
        1. Table 6-1 GP-ADC Parameter
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Reference Schematic
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
      3. 7.3.3 Stackup Details
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
  • ALA|209
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 5-7 SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input)(1)(2)(3)

NO. PARAMETER MIN TYP MAX UNIT
1 tc(SPC)M Cycle time, SPICLK(4) 25 256tc(VCLK) ns
2(4) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 4 0.5tc(SPC)M + 4 ns
tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 4 0.5tc(SPC)M + 4
3(4) tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 4 0.5tc(SPC)M + 4 ns
tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 4 0.5tc(SPC)M + 4
4(4) td(SPCH-SIMO)M Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0) 0.5tc(SPC)M – 3 ns
td(SPCL-SIMO)M Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1) 0.5tc(SPC)M – 3
5(4) tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0) 0.5tc(SPC)M – 10.5 ns
tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1) 0.5tc(SPC)M – 10.5
6(5) tC2TDELAY Setup time CS active until SPICLK high
(clock polarity = 0)
CSHOLD = 0 (C2TDELAY+2)*tc(VCLK) – 7.5 (C2TDELAY+2) * tc(VCLK) + 7 ns
CSHOLD = 1 (C2TDELAY +3) * tc(VCLK) – 7.5 (C2TDELAY+3) * tc(VCLK) + 7
Setup time CS active until SPICLK low
(clock polarity = 1)
CSHOLD = 0 (C2TDELAY+2)*tc(VCLK) – 7.5 (C2TDELAY+2) * tc(VCLK) + 7
CSHOLD = 1 (C2TDELAY +3) * tc(VCLK) – 7.5 (C2TDELAY+3) * tc(VCLK) + 7
7(5) tT2CDELAY Hold time, SPICLK low until CS inactive (clock polarity = 0) 0.5*tc(SPC)M + (T2CDELAY + 1) *tc(VCLK) – 7 0.5*tc(SPC)M + (T2CDELAY + 1) * tc(VCLK) + 7.5 ns
Hold time, SPICLK high until CS inactive (clock polarity = 1) 0.5*tc(SPC)M + (T2CDELAY + 1) *tc(VCLK) – 7 0.5*tc(SPC)M + (T2CDELAY + 1) * tc(VCLK) + 7.5
8(4) tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
5 ns
tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
5
9(4) th(SPCL-SOMI)M Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
3 ns
th(SPCH-SOMI)M Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
3
The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared (where x= 0 or 1).
tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25ns.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
IWR6843 SPI_master_mode_external_timing_phase0.gifFigure 5-3 SPI Master Mode External Timing (CLOCK PHASE = 0)
IWR6843 SPI_master_mode_chip_select_phase0.gifFigure 5-4 SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)