SNOSD01D May 2015 – October 2016 LDC1101
The LDC1101 requires minimal external components for effective operation. Following good layout techniques providing good grounding and clean supplies are critical for optimum operation. Due to the small physical size of the LDC1101, use of surface mount 0402 or smaller components can ease routing.
Ground and power planes are helpful for maintaining a clean supply to the LDC1101. In the layout shown in Figure 61, a top-layer ground fill is also used for improved grounding.
The CLKIN pin routing must maintain consistent impedance; typically this is 50 Ω, but can be adjusted based on board geometries. If a parallel termination resistor is used, it must be placed as close to the CLKIN pin as possible. Minimize layer changes and routing through vias for the CLKIN signal. Maintain an uninterrupted ground plane under the trace.
The capacitor CLDO must be placed as close to the CLDO pin as possible.
Place the bypass capacitors as close to the VDD pin as possible, with the smaller valued capacitor placed closer.
The sensor capacitor must be as close to the sensor inductor as possible. The INA and INB traces must be routed in parallel and as close to each other as possible to minimize coupling of noise. If cable is to be used, then INA and INB should be a twisted pair or in coaxial cable. The distance between the INA/INB pins and the sensor affects the maximum possible sensor frequency. For some applications, it may be helpful to place small-value capacitor (for example, 10 pF) from INA to ground and INB to ground; these capacitors should be located close to the INA and INB pins.
Refer to Application Note LDC Sensor Design (SNOA930) for additional information on sensor design.