SNVS586O September 2008 – November 2014 LM22673 , LM22673-Q1

PRODUCTION DATA.

- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Applications and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information

- DDA|8

The LM22673 device incorporates a voltage mode constant frequency PWM architecture. In addition, input voltage feedforward is used to stabilize the loop gain against variations in input voltage. This allows the loop compensation to be optimized for transient performance. The power MOSFET, in conjunction with the diode, produce a rectangular waveform at the switch pin, that swings from about zero volts to VIN. The inductor and output capacitor average this waveform to become the regulator output voltage. By adjusting the duty cycle of this waveform, the output voltage can be controlled. The error amplifier compares the output voltage with the internal reference and adjusts the duty cycle to regulate the output at the desired value.

The internal loop compensation of the -ADJ option is optimized for outputs of 5V and below. If an output voltage of 5V or greater is required, the -5.0 option can be used with an external voltage divider. The minimum output voltage is equal to the reference voltage, that is, 1.285 V (typ).

The LM22673 also incorporates an input undervoltage lock-out (UVLO) feature. This prevents the regulator from turning on when the input voltage is not great enough to properly bias the internal circuitry. The rising threshold is 4.3 V (typ) while the falling threshold is 3.9 V (typ).

The soft-start feature allows the regulator to gradually reach steady-state operation, thus reducing start-up stresses. The internal soft-start feature brings the output voltage up in about 500 µs. This time can be extended by using an external capacitor connected to the SS pin. Values in the range of 100 nF to 1 µF are recommended. The approximate soft-start time can be estimated from Equation 1.

Equation 1.

Soft-start is reset any time the part is shut down or a thermal overload event occurs.

The LM22673 incorporates a floating high-side gate driver to control the power MOSFET. The supply for this driver is the external boot-strap capacitor connected between the BOOT pin and SW. A good quality 10 nF ceramic capacitor must be connected to these pins with short, wide PCB traces. One reason the regulator imposes a minimum off-time is to ensure that this capacitor recharges every switching cycle. A minimum load of about 5 mA is required to fully recharge the boot-strap capacitor in the minimum off-time. Some of this load can be provided by the output voltage divider, if used.

The LM22673 has internal loop compensation designed to provide a stable regulator over a wide range of external power stage components. The internal compensation of the -ADJ option is optimized for output voltages below 5 V. If an output voltage of 5 V or greater is needed, the -5.0 option with an external resistor divider can be used.

Ensuring stability of a design with a specific power stage (inductor and output capacitor) can be tricky. The LM22673 stability can be verified using the WEBENCH Designer online circuit simulation tool. A quick start spreadsheet can also be downloaded from the online product folder.

The complete transfer function for the regulator loop is found by combining the compensation and power stage transfer functions. The LM22673 has internal type III loop compensation, as detailed in Figure 10. This is the approximate "straight line" function from the FB pin to the input of the PWM modulator. The power stage transfer function consists of a dc gain and a second order pole created by the inductor and output capacitor(s). Due to the input voltage feedforward employed in the LM22673, the power stage dc gain is fixed at 20 dB. The second order pole is characterized by its resonant frequency and its quality factor (Q). For a first pass design, the product of inductance and output capacitance should conform to Equation 2.

Equation 2.

Alternatively, this pole should be placed between 1.5 kHz and 15 kHz and is given by Equation 3.

Equation 3.

The Q factor depends on the parasitic resistance of the power stage components and is not typically in the control of the designer. Of course, loop compensation is only one consideration when selecting power stage components (see the *Applications and Implementation* section for more details).

In general, hand calculations or simulations can only aid in selecting good power stage components. Good design practice dictates that load and line transient testing should be done to verify the stability of the application. Also, Bode plot measurements should be made to determine stability margins. *AN-1889 How to Measure the Loop Transfer Function of Power Supplies* (SNVA364) shows how to perform a loop transfer function measurement with only an oscilloscope and function generator.

The LM22673 has current limiting to prevent the switch current from exceeding safe values during an accidental overload on the output. This peak current limit is found in the *Electrical Characteristics* table under the heading of I_{CL}. The maximum load current that can be provided, before current limit is reached, is determined from Equation 4.

Equation 4.

Where:

L is the value of the power inductor.

When the LM22673 enters current limit, the output voltage will drop and the peak inductor current will be fixed at I_{CL} at the end of each cycle. The switching frequency will remain constant while the duty cycle drops. The load current will not remain constant, but will depend on the severity of the overload and the output voltage.

For very severe overloads ("short-circuit"), the regulator changes to a low frequency current foldback mode of operation. The frequency foldback is about 1/5 of the nominal switching frequency. This will occur when the current limit trips before the minimum on-time has elapsed. This mode of operation is used to prevent inductor current "run-away", and is associated with very low output voltages when in overload. Equation 5 can be used to determine what level of output voltage will cause the part to change to low frequency current foldback.

Equation 5.

Where:

F_{sw} is the normal switching frequency.

V_{in} is the maximum for the application.

If the overload drives the output voltage to less than or equal to V_{x}, the part will enter current foldback mode. If a given application can drive the output voltage to ≤ V_{x}, during an overload, then a second criterion must be checked. Equation 6 gives the maximum input voltage, when in this mode, before damage occurs.

Equation 6.

Where:

V_{sc} is the value of output voltage during the overload.

f_{sw} is the normal switching frequency.

NOTE

If the input voltage should exceed this value, while in foldback mode, the regulator and/or the diode may be damaged.

It is important to note that the voltages in Equation 4 through Equation 6 are measured at the inductor. Normal trace and wiring resistance will cause the voltage at the inductor to be higher than that at a remote load. Therefore, even if the load is shorted with zero volts across its terminals, the inductor will still see a finite voltage. It is this value that should be used for V_{x} and V_{sc} in the calculations. In order to return from foldback mode, the load must be reduced to a value much lower than that required to initiate foldback. This load "hysteresis" is a normal aspect of any type of current limit foldback associated with voltage regulators.

The safe operating area, when in short circuit mode, is shown in Figure 11. Operating points below and to the right of the curve represent safe operation.

A key feature of the LM22673 is the ability to adjust the peak switch current limit. This can be useful when the full current capability of the regulator is not required for a given application. A smaller current limit may allow the use of power components with lower current ratings, thus saving space and reducing cost. A single resistor between the IADJ pin and ground controls the current limit in accordance with Figure 12. The current limit mode is set during start-up of the regulator. When V_{IN} is applied, a weak pullup is connected to the IADJ pin and, after approximately 100 µs, the voltage on the pin is checked against a threshold of about 0.8V. With the IADJ pin open, the voltage floats above this threshold, and the current limit is set to the default value of 4.2A (typ). With a resistor present, an internal reference holds the pin voltage at 0.8 V; the resulting current sets the current limit. The accuracy of the adjusted current limit will be slightly worse than that of the default value, that is, +35% / –25% is to be expected. Resistor values should not exceed the limits shown in Figure 12.

Internal thermal shutdown circuitry protects the LM22673 should the maximum junction temperature be exceeded. This protection is activated at about 150°C, with the result that the regulator will shutdown until the temperature drops below about 135°C.

Ideally the regulator would control the duty cycle over the full range of zero to one. However due to inherent delays in the circuitry, there are limits on both the maximum and minimum duty cycles that can be reliably controlled. This in turn places limits on the maximum and minimum input and output voltages that can be converted by the LM22673. A minimum on-time is imposed by the regulator in order to correctly measure the switch current during a current limit event. A minimum off-time is imposed in order the re-charge the bootstrap capacitor. Equation 7 can be used to determine the approximate maximum input voltage for a given output voltage.

Equation 7.

Where:

F_{sw} is the switching frequency.

T_{ON} is the minimum on-time.

Both parameters are found in the *Electrical Characteristics* table.

Nominal values should be used. The worst case is lowest output voltage. If this input voltage is exceeded, the regulator will skip cycles, effectively lowering the switching frequency. The consequences of this are higher output voltage ripple and a degradation of the output voltage accuracy.

The second limitation is the maximum duty cycle before the output voltage will "dropout" of regulation. Equation 8 can be used to approximate the minimum input voltage before dropout occurs.

Equation 8.

Where:

The values of T_{OFF} and R_{DS(ON)} are found in the *Electrical Characteristics* table.

The worst case here is largest load. In this equation, R_{L} is the dc inductor resistance. Of course, the lowest input voltage to the regulator must not be less than 4.5 V (typ).