SNVS586O September   2008  – November 2014 LM22673 , LM22673-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Handling Ratings: LM22673-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 UVLO
      2. 7.3.2 Soft-Start
      3. 7.3.3 Boot-Strap Supply
      4. 7.3.4 Internal Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Current Limit
      2. 7.4.2 Current-Limit Adjustment
      3. 7.4.3 Thermal Protection
      4. 7.4.4 Duty-Cycle Limits
  8. Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Voltage Divider Selection
      2. 8.1.2 Power Diode
    2. 8.2 Typical Application
      1. 8.2.1 Typical Buck Regulator Application
        1. Design Requirements
        2. Detailed Design Procedure
          1. External Components
          2. Inductor
          3. Input Capacitor
          4. Output Capacitor
          5. Boot-Strap Capacitor
        3. Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

Board layout is critical for the proper operation of switching power supplies. First, the ground plane area must be sufficient for thermal dissipation purposes. Second, appropriate guidelines must be followed to reduce the effects of switching noise. Switch mode converters are very fast switching devices. In such cases, the rapid increase of input current combined with the parasitic trace inductance generates unwanted L di/dt noise spikes. The magnitude of this noise tends to increase as the output current increases. This noise may turn into electromagnetic interference (EMI) and can also cause problems in device performance. Therefore, care must be taken in layout to minimize the effect of this switching noise.

The most important layout rule is to keep the ac current loops as small as possible. Figure 16 shows the current flow in a buck converter. The top schematic shows a dotted line which represents the current flow during the FET switch on-state. The middle schematic shows the current flow during the FET switch off-state.

The bottom schematic shows the currents referred to as ac currents. These ac currents are the most critical because they are changing in a very short time period. The dotted lines of the bottom schematic are the traces to keep as short and wide as possible. This will also yield a small loop area reducing the loop inductance. To avoid functional problems due to layout, review the PCB layout example. Best results are achieved if the placement of the LM22673, the bypass capacitor, RFFB, RFBT, the Schottky diode and the inductor are placed as shown in the example. In the layout shown, R1 = RFBB and R2 = RFBT. It is also recommended to use 2 oz copper boards or heavier to help thermal dissipation and to reduce the parasitic inductances of board traces. See AN-1229 SIMPLE SWITCHER ® PCB Layout Guidelines (SNVA054) for more information.

30076224.gifFigure 16. Current Flow in a Buck Application

10.2 Layout Examples

30076225.pngFigure 17. PCB Layout Example for PFM Package
30076241.pngFigure 18. PCB Layout Example for SO PowerPAD Package

10.3 Thermal Considerations

The components with the highest power dissipation are the power diode and the power MOSFET internal to the LM22673 regulator. The easiest method to determine the power dissipation within the LM22673 is to measure the total conversion losses then subtract the power losses in the diode and inductor. The total conversion loss is the difference between the input power and the output power. An approximation for the power diode loss is shown in Equation 16.

Equation 16. 30076069.gif


VD is the diode voltage drop.

An approximation for the inductor power is determined by Equation 17.

Equation 17. 30076084.gif


RL is the dc resistance of the inductor.

The 1.1 factor is an approximation for the ac losses.

The regulator has an exposed thermal pad to aid power dissipation. Adding multiple vias under the device to the ground plane will greatly reduce the regulator junction temperature. Selecting a diode with an exposed pad will also aid the power dissipation of the diode. The most significant variables that affect the power dissipation of the regulator are output current, input voltage and operating frequency. The power dissipated while operating near the maximum output current and maximum input voltage can be appreciable. The junction-to-ambient thermal resistance of the LM22673 will vary with the application. The most significant variables are the area of copper in the PC board, the number of vias under the IC exposed pad and the amount of forced air cooling provided. A large continuos ground plane on the top or bottom PCB layer will provide the most effective heat dissipation. The integrity of the solder connection from the IC exposed pad to the PC board is critical. Excessive voids will greatly diminish the thermal dissipation capacity. The junction-to-ambient thermal resistance of the LM22673 SO PowerPAD package, and the PFM package, are specified in the Electrical Characteristics table. See AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419) for more information.