SNVS859C July   2012  – September 2016 LM25101

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Start-Up and UVLO
      2. 8.3.2 Level Shift
      3. 8.3.3 Output Stages
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting External Gate Driver Resistor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

The optimum performance of high and low-side gate drivers cannot be achieved without following certain guidelines during circuit-board layout.

  • Low ESR and ESL capacitors must be connected close to the IC, between the VDD and VSS pins and between the HB and HS pins to support the high peak currents being drawn from VDD during start-up of the external MOSFET.
  • To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be connected between the MOSFET drain and ground (VSS).
  • To avoid large negative transients on the switch node (HS pin), the parasitic inductances must be minimized in the source of the top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier).
  • Grounding Considerations:
    • The first priority in designing grounding connections is to confine to a minimal physical area the high peak currents that charge and discharge the MOSFET gate. This decreases the loop inductance and minimizes noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as possible to the gate driver.
    •  The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor, and low-side MOSFET body diode. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.

Figure 26 shows a recommended layout pattern for the driver. If possible a single layer placement is preferred.

11.2 Layout Example

LM25101 30192938.gif Figure 26. Recommended Layout Pattern