7.3.1 Detailed Pin Description

7.3.2 Start-Up

Referring to Figure 8, when the AC rectified line voltage is applied to the bulk-energy-storage capacitor; the N-channel depletion mode MOSFET is turned on and supplies the charging current to the VCC capacitor. When the voltage on the VCC pin reaches 12.5-V typical, the PWM controller, soft-start circuit and gate driver are enabled.

When the LM5023 is enabled and the OUT drive signal starts switching the flyback MOSFET, energy is being stored and then transferred from the transformer primary to the secondary windings. A bias winding, shown in Figure 8, delivers energy to the VCC capacitor to sustain the voltage on the VCC pin. The voltage supplied from the auxiliary winding should be within the range of 10 V to 14 V (where 16 V is the absolute maximum rating).

After reaching the VCC_ON threshold, the LM5023 VSD open drain output, which is pulled up to VCC during start-up, goes low. This applies a negative gate to source voltage on the depletion mode MOSFET turning it off. This disables the high-voltage start-up circuit. The high-voltage start-up circuit can be implemented in either of two ways; the first is shown in Figure 8, which uses an N-channel depletion modle FET, the second is shown in Figure 9, which uses an N-channel enhancement mode FET. The circuit using the depletion mode FET will have the lowest standby power. The standby power consumption of the FET is the voltage across the start-up FET multiplied by the drain-to-source cutoff current with gate negatively biased, this is typically 0.1 µA.

Standby power of the start-up FET calculation is shown in Equation 1 through Equation 5.

Equation 1.

Equation 2.

Equation 3.

Equation 4.

where

• I_D(off) is the depletion mode FETs leakage current

Equation 5.

When VCC < VCC_ON the standby current consumption of the IC = I_CC(st), nominally 340 µA.

Figure 8. Start-Up With a Depletion Mode FET

An alternative start-up circuit employs an enhancement mode FET with pull-up resistors connected from the rectified DC bus to the gate of the FET, Figure 9. After the input AC power is applied, the enhancement mode FET supplies the charging current to the VCC capacitor C_VCC. After reaching the VCC_ON threshold, the LM5023 VSD open drain output, which is pulled up to VCC during start-up, goes low. This grounds the gate of the start-up MOSFET, turning it off. The start-up resistors are always in the circuit, therefore the standby power consumed will be higher than if a depletion mode FET were used.

Equation 6.

Equation 7.

Equation 8.

Equation 9.

Equation 10.

Figure 9. Start-Up With an Enhancement Mode FET

7.3.3 Quasi-Resonant Operation

A quasi-resonant controlled flyback converter operates by storing energy in the transformer's primary during the MOSFET's on-time. During the on-time (t_ON) V_IN is applied across the primary of the transformer. The primary current starts out at zero and ramps towards a peak value (I_PEAK). When the peak-primary current reaches the feedback compensation error voltage the PWM comparator resets the output drive, turning off the MOSFET. Due to the phasing of the transformer, the output diode is reverse-biased during the MOSFET on-time.

During the MOSFET's off time the output diode is forward biased and the stored energy in the transformer primary inductor is transferred to the output. The voltage seen on the secondary winding is V_OUT plus the output diode's forward voltage drop, V_F. The current in the secondary winding linearly decreases from I_PEAK × Np/Ns to zero, refer to Figure 11.

When the current in the secondary reaches zero, the transformer is demagnetized, and there is an open circuit on the secondary, and with the primary MOSFET also turned off, there is an open on the primary. A resonant circuit is formed between the transformers primary inductance and the MOSFET output capacitance. The resonant frequency is calculated by Equation 11.

Equation 11.

During the resonant period the drain voltage of the MOSFET will ring down towards ground, refer to Figure 10. When the drain voltage is at its minimum the flyback MOSFET is turned back on. The point where the voltage is at its minimum is calculated by Equation 12.

Equation 12.

Figure 10. The Flyback Drain Voltage Waveform

Transformer demagnetization is detected by sensing the transformers auxiliary winding. When the transformer is demagnetized the auxiliary winding voltage follows the drain of the MOSFET and changes from V_OUT × N_AUX/Ns to –V_IN × N_AUX/Np. Internal to the LM5203 QR pin is a comparator with a 0.35-V reference. As the auxiliary-winding voltage falls below 0.35 V, the voltage is sensed and the comparator sets the PWM flip-flop turning on the flyback MOSFET. Figure 11 shows the QR converter typical waveforms; the auxiliary winding voltage, and primary and secondary current waveforms. It is possible to adjust the delay on the auxiliary winding with a resistor and external capacitor to ensures that the MOSFET switches when its drain voltage is at its minimum. Refer to the schematic in Figure 15 and the section on Valley Switching for details. The benefits of QR operation are reduced EMI, and reduced turn-on switching losses.

Figure 11. QR Converter Typical Waveforms

7.3.4 Quasi-Resonant Operating Frequency

When the primary-side flyback MOSFET turns on, the current ramps up until the peak-primary current exceeds the feedback compensation error voltage. When this occurs the PWM comparator resets the output drive, turning off the MOSFET. The current ramps up with a slope shown in Equation 13.

Equation 13.

The t_ON time of the switch is calculated by Equation 14.

Equation 14.

When the primary-side flyback MOSFET is turned off, the energy stored in the primary inductance is transfer to the secondary inductance, the off time to transfer all of the energy is shown in Equation 15.

Equation 15.

where

• N_SP = N_S/N_P

The total switching period is shown in Equation 15.

Equation 16.

The resonant circuit created by the transformer primary inductance and the MOSFETs switch node capacitance is the t_DLY time, refer to Figure 11.

Equation 17.

Equation 18.

Equation 19 represents the relationship of switching frequency, L_P, and N_PS.

Equation 19.

The QR flyback converter does not operate at a fixed frequency. The frequency varies with the output load, input line voltage, or a combination of the two. In order to keep LM5023 frequency below the EMI starting limit of 150 kHz per CISPR--22, the LM5023 has an internal timer which prevents the output drive from restarting within 7.69 μs of the previous driver output (OUT) low-to-high transition. This timer clamps the maximum switching frequency at 130 kHz (typical).

7.3.5 PWM Comparator

The PWM comparator compares the current sense signal with the loop error voltage from the COMP pin. The COMP pin voltage is reduced by a fixed 0.75-V offset and then attenuated by a 3:1 resistor divider. The PWM comparator input offset voltage is designed such that less than 0.75 V at the COMP pin will result in a zero duty cycle at the controller output.

7.3.6 Soft-Start

The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thereby reducing start-up stresses and current surges. At power on, after the VCC reaches the VCC_ON threshold, an internal 22-μA current source charges an external capacitor connected to the SS pin. The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and the duty cycle of the output pulses.

7.3.7 Gate Driver

The LM5023 driver (OUT) was designed to drive the gate of an N-channel MOSFET and is capable of sourcing a peak current of 0.4 A and sinking 0.7 A.

Figure 12. LM5023 Modulation Curve

7.3.8 Current Limit and Current Sense

The LM5023 provides a cycle-by-cycle over current protection feature. Current limit is triggered by an internal current sense comparator with a threshold of 500 mV. If the CS pin voltage plus the current limit feedforward signal voltage exceeds 500 mV, the MOSFET drive signal (OUT) will be terminated. An RC filter, located near the LM5023 CS pin is recommended to attenuate the noise coupled from the power FET’s gate to source switching. The CS pin capacitance is discharged at the end of each PWM cycle by an internal switch. The discharge switch remains on for an additional 130 ns for leading edge blanking (LEB). LEB prevents the LM5023 current sense comparator from being falsely triggered due to the noise generated by the switch currents initial spike. The LM5023 current sense comparator is very fast and may respond to short-duration noise pulses. Layout considerations are critical for the current-sense filter and sense resistor. The capacitor associated with the CS filter must be placed very close to the device and connected directly to the pins of the device (CS and GND). If a current sense transformer is used, both leads of the transformer secondary should be routed to the sense resistor, which should also be located close to the device. If a current sense resistor located in the power FET’s source is used for current sense, a low inductance resistor is required. In this case, all of the noise-sensitive low-current grounds should be connected in common near the device and then a single connection should be made.