SNVSAP6 September   2017 LM5150-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable (EN Pin)
      2. 7.3.2  High Voltage VCC Regulator (PVCC, AVCC Pin)
      3. 7.3.3  Power-On Voltage Selection (VSET Pin)
      4. 7.3.4  Switching Frequency (RT Pin)
      5. 7.3.5  Clock Synchronization (SYNC Pin in SS Configuration)
      6. 7.3.6  Current Sense, Slope Compensation, and PWM (CS Pin)
      7. 7.3.7  Current Limit (CS Pin)
      8. 7.3.8  Feedback and Error Amplifier (COMP Pin)
      9. 7.3.9  Automatic Wake-Up and Standby
      10. 7.3.10 Boost Status Indicator (STATUS Pin)
      11. 7.3.11 Maximum Duty Cycle Limit, Minimum Input Supply Voltage
      12. 7.3.12 MOSFET Driver (LO Pin)
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Wake-Up Mode
        1. 7.4.3.1 Start-Stop Configuration (SS Configuration)
        2. 7.4.3.2 Emergency-Call Configuration (EC Configuration)
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bypass Switch / Disconnection Switch Control
      2. 8.1.2 Loop Response
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  RSET Resistor
        3. 8.2.2.3  RT Resistor
        4. 8.2.2.4  Inductor Selection (LM)
        5. 8.2.2.5  Current Sense (RS)
        6. 8.2.2.6  Slope Compensation Ramp (RSL)
        7. 8.2.2.7  Output Capacitor (COUT)
        8. 8.2.2.8  Loop Compensation Component Selection and Maximum ESR
        9. 8.2.2.9  PVCC Capacitor, AVCC Capacitor, and AVCC Resistor
        10. 8.2.2.10 VOUT Filter (CVOUT, RVOUT)
        11. 8.2.2.11 Input Capacitor
        12. 8.2.2.12 MOSFET Selection
        13. 8.2.2.13 Diode Selection
        14. 8.2.2.14 Efficiency Estimation
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Lower Standby Threshold in SS Configuration
      2. 8.3.2 Dithering Using Dither Enabled Device
      3. 8.3.3 Clock Synchronization With LM5140
      4. 8.3.4 Dynamic Frequency Change
      5. 8.3.5 Dithering Using an External Clock
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RUM|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The LM5150-Q1 is a non-synchronous boost controller. The following design procedure can be used to select the external components for the LM5150-Q1. Alternately, the WEBENCH® software may be used to generate complete designs. The WEBENCH software uses an iterative design procedure and accesses comprehensive data bases of components when generating a design. This section presents a simplified discussion of the design process.

Bypass Switch / Disconnection Switch Control

The STATUS pin can be used to control an external bypass switch, which turns on when the boost is in standby mode, or to control an external disconnection switch that turns off when the boost is in standby mode. In Figure 17, a P-channel MOSFET is used to connect the boost supply input to the load directly when the boost is in standby mode. This bypass switch can be turned on slowly, but it must be turned off fast after the STATUS pin is pulled up by the wake-up event. The STATUS pin is rated to the absolute maximum 65 V.

LM5150-Q1 Fig17N.gif Figure 17. Bypass Switch Control Example

In Figure 18, a P-channel MOSFET is used to disconnect the boost supply output from the battery when boost is not required. This disconnection switch can be turned off slowly, but it must be turned on fast after the STATUS pin is pulled up by the wake-up event.

LM5150-Q1 Fig18N.gif Figure 18. Disconnection Switch Control Example

Loop Response

The open-loop transfer function of a boost regulator is defined as the product of modulator transfer function and feedback transfer function.

The modulator transfer function of a current mode boost regulator including a power stage with an embedded current loop can be simplified as a one load pole (FLP), one ESR zero (FZ_ESR), and one Right Half Plane (RHP) zero (FRHP) system, which can be explained as follows.

Modulator transfer function is defined as follows:

Equation 15. LM5150-Q1 eq_16_SNVSAP6.gif

where

  • LM5150-Q1 eq_17_SNVSAP6.gif
  • LM5150-Q1 eq_18_SNVSAP6.gif
  • LM5150-Q1 eq_19_SNVSAP6.gif
  • LM5150-Q1 eq_20_SNVSAP6.gif

RESR is the equivalent series resistance (ESR) of the output capacitor which is specified in the capacitor datasheet.

RCOMP, CCOMP and CHF (see Figure 19) configure the error amplifier gain and phase characteristics to produce a stable voltage loop with fast response. This compensation network creates a dominant pole at low frequency (FDP_EA), a mid-band zero (FZ_EA), and a high frequency pole (FP_EA).

The feedback transfer function is defined as follows:

Equation 16. LM5150-Q1 eq_21_SNVSAP6.gif

where

  • LM5150-Q1 eq_22_SNVSAP6.gif
  • LM5150-Q1 eq_23_SNVSAP6.gif
  • LM5150-Q1 eq_24_SNVSAP6.gif
  • LM5150-Q1 eq_25_SNVSAP6.gif

RO (≈ 10 MΩ) is the output resistance of the error amplifier and Gm (≈ 2 mA/V) is the transconductance of the error amplifier.

Assuming FLP is canceled by FZ_EA, FRHP is much higher than crossover frequency (FCROSS), and FZ_ESR is either canceled by FP_EA or FZ_ESR is much higher than FCROSS, the open-loop transfer function can be simplified as follows:

Equation 17. LM5150-Q1 eq_27_SNVSAP6.gif

Because |T(s)|=1 at the crossover frequency, the crossover frequency can be simply estimated using those assumptions.

Equation 18. LM5150-Q1 eq_28_SNVSAP6.gif

Typical Application

The LM5150-Q1 requires a minimum number of external components to work. Figure 19 includes all optional components as an example.

LM5150-Q1 Fig19N.gif Figure 19. Typical Circuit With Optional Components

Design Requirements

Table 6 lists the design parameters for Figure 19.

Table 6. Design Example Parameters

DESIGN PARAMETER VALUE
Target Application Start-stop
Minimum Input Supply Voltage (VSUPPLY(MIN)) 2.5 V
Target Output Voltage (VLOAD) 8.5 V
Maximum Load Current (ILOAD) 2.94 A (≈ 25 Watt)
Switching Frequency (FSW) 440 kHz
D1 Diode Forward Voltage Drop 0.7 V
Maximum Inductor Current Ripple Ratio (RR) 0.6 (= 60%)
Estimated Full Load Efficiency (Eff) 0.8 (= 80%)
Current Limit Margin (MCL) 1.2 (= 120%)
FLP over FCROSS (K1) 0.15 (FLP = 0.15 × FCROSS)
FZ_EA over FLP (K2) 3 (FZ_EA = 3 × FLP)

Detailed Design Procedure

Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5150-Q1 device with the WEBENCH® Power Designer.

  1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
  2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
  3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

  • Run electrical simulations to see important waveforms and circuit performance
  • Run thermal simulations to understand board thermal performance
  • Export customized schematic and layout into popular CAD formats
  • Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

RSET Resistor

Select the value of RSET, referring to Table 1. 9.53 kΩ is chosen to target 8.5 V in SS configuration. In general, about 5% to approximately 10% output undershoot should be considered when selecting the VOUT regulation target.

RT Resistor

The value of RT for 440-kHz switching frequency is calculated as follows:

Equation 19. LM5150-Q1 LM5150-Q1-equation-02-snvsap6.gif

A standard value of 49.9 kΩ is chosen for RT.

In general, higher frequency boost converters are smaller and faster, but they also have higher switching losses and lower efficiency.

Inductor Selection (LM)

When selecting the inductor, consider three key parameters: inductor current ripple ratio (RR), falling slope of the inductor current, and RHP zero frequency (FRHP).

Inductor current ripple ratio is selected to have a balance between core loss and copper loss. The falling slope of the inductor current must be low enough to prevent sub-harmonic oscillation at high duty cycle (additional RSL resistor is required if not). Higher FRHP (= lower inductance) allows a higher crossover frequency and is always preferred when using a smaller value output capacitor.

The inductance value can be selected to set the inductor current ripple between 30% and 70% of the average inductor current as a good compromise between RR, FRHP and inductor falling slope. In this example, 60% ripple ratio (RR = 0.6) is selected as the maximum inductor current ripple ratio (the inductor current ripple ratio is the biggest when D = 0.33). The target inductance value is calculated as follows:

Equation 20. LM5150-Q1 eq_30_SNVSAP6.gif
Equation 21. LM5150-Q1 eq_31_SNVSAP6.gif

If the target inductance is smaller than the value calculated using Equation 21, consider adding the slope compensation resistor (RSL), as mentioned in the Slope Compensation Ramp (RSL) section, or select a smaller RR and recalculate the inductance using Equation 20.

A standard value of 1.5 µH is chosen for LM. The required inductor saturation current rating is estimated after selecting RS and RSL.

Current Sense (RS)

Based on the assumptions that 20% of current limit margin (MCL = 1.2), 80% estimated efficiency (Eff = 0.8) at full load and no RSL populated, RS is calculated using Equation 22 and Equation 23.

Equation 22. LM5150-Q1 eq_32_SNVSAP6.gif
Equation 23. LM5150-Q1 eq_33_SNVSAP6.gif

Substitute FSW_RT for FSYNC if the clock synchronization is not used.

A standard value of 7 mΩ is chosen for RS. A low-ESL resistor is recommended to minimize the error caused by the ESL.

Slope Compensation Ramp (RSL)

The minimum inductance value which can prevent sub-harmonic oscillation without RSL is calculated using Equation 24. If the selected inductance value is less than the minimum inductance calculated using Equation 24, add a slope compensation resistor (RSL) externally.

Equation 24. LM5150-Q1 eq_34_SNVSAP6.gif

1.2 is the recommended margin to cover non-ideal factors.

If needed, use Equation 25 to find the RSL value which matches the typical amount of slope compensation.

Equation 25. LM5150-Q1 eq_35_SNVSAP6.gif

In this example, RSL is not populated because the selected inductance value, 1.5 µH, is greater than the minimum required inductance from Equation 24.

After selecting RS and RSL, the peak inductor current at current limit (IPEAK-CL) can be calculated. Setting the inductor saturation current rating higher than the IPEAK-CL is recommended.

Equation 26. LM5150-Q1 eq_36_SNVSAP6.gif
Equation 27. LM5150-Q1 eq_37_SNVSAP6.gif

TD is the typical propagation delay of current limit.

Output Capacitor (COUT)

There are a few ways to select the proper value of output capacitor (COUT). The output capacitor value can be selected based on output voltage ripple, output overshoot or undershoot due to load transient. In this example, COUT is selected based on output undershoot because the waking up performance is similar with no-load to full-load transient performance.

The output undershoot becomes smaller by increasing FCROSS or by decreasing FLP: a smaller COUT is allowed by increasing FCROSS or by decreasing FLP.

To increase FCROSS, FSW and FRHP must be increased because the maximum FCROSS is, in general, limited at 1/10 of FRHP at VSUPPLY(MIN) or 1/10 of FSW whichever is lower.

FRHP is calculated using Equation 28.

Equation 28. LM5150-Q1 eq_38_SNVSAP6.gif

FCROSS is selected at 1/10 of FRHP or 1/10 of FSW, whichever is lower.

Equation 29. LM5150-Q1 LM5150-Q1-equation-03-snvsap6.gif
Equation 30. LM5150-Q1 LM5150-Q1-equation-04-snvsap6.gif

In this example, 2.27 kHz is selected as a target FCROSS and FLP is selected to be 340 Hz (K1 = 0.15).

In general, there is about 5% or less undershoot with FLP = 0.1 × FCROSS (K1 = 0.1) and 10% or less undershoot with FLP = 0.2 × FCROSS (K1 = 0.2) during 0% to 100% load transient. The recommended K1 factor range is from 0.02 to 0.2.

FLP is calculated using Equation 31.

Equation 31. LM5150-Q1 eq_41_SNVSAP6.gif

The minimum required output capacitance value is calculated using Equation 32.

Equation 32. LM5150-Q1 LM5150-Q1-equation-05-snvsap6.gif

The maximum output ripple current is calculated at the minimum input supply voltage as follows:

Equation 33. LM5150-Q1 eq_43_SNVSAP6.gif

The ripple current rating of the output capacitors must be enough to handle the output ripple current. By using multiple output capacitors, the ripple current can be split. In practice, ceramic capacitors are placed closer to the diode and the MOSFET than the bulk aluminum capacitors in order to absorb the majority of the ripple current.

In this example, three 100-µF capacitors are placed in parallel to ensure ripple current capability. If high-ESR capacitors are used for the output capacitor, additional 10-µF ceramic capacitors can be placed close to the switching components to minimize switching noise.

Loop Compensation Component Selection and Maximum ESR

Based on Equation 18, CCOMP is calculated as follows:

Equation 34. LM5150-Q1 eq_44_SNVSAP6.gif
Equation 35. LM5150-Q1 LM5150-Q1-equation-06-snvsap6.gif

By selecting CCOMP following Equation 34, the typical phase margin is set to 90⁰ and the loop response is overdamped. In this example, FZ_EA is placed at 3 times higher frequency than FLP to have lower phase margin but faster settling time (K2 = 3, target FZ_EA is 1.02 kHz). Recommended range of FZ_EA is from 1 × FLP to 4 × FLP (1 ≤ K2 ≤ 4). Practical crossover frequency will vary with K2 with a range of 0.5 × FCROSS to 1.0 × FCROSS.

Equation 36. LM5150-Q1 LM5150-Q1-equation-07-snvsap6.gif

A standard value of 33 nF is chosen for CCOMP.

RCOMP is selected to set the error amplifier zero at 1.02 kHz.

Equation 37. LM5150-Q1 LM5150-Q1-equation-08-snvsap6.gif

A standard value of 4.64 kΩ is chosen for RCOMP.

CHF is usually used to create a pole at high frequency (FP_EA) to cancel FZ_ESR. By using a small ESR capacitor which can place FZ_ESR greater than 10 × FCROSS, the output capacitor ESR would not affect the loop stability. The maximum ESR which does not affect the loop response is calculated using Equation 38.

Equation 38. LM5150-Q1 LM5150-Q1-equation-09-snvsap6.gif

PVCC Capacitor, AVCC Capacitor, and AVCC Resistor

The PVCC capacitor supplies the peak transient current to the LO driver. The value of PVCC capacitor (CPVCC) must be 4.7 μF or higher and must be a high-quality, low-ESR, ceramic capacitor. CPVCC must be placed close to the PVCC pin and the PGND pin. A value of 4.7 μF is selected for this design example. The AVCC capacitor must be placed close to the device. The recommended AVCC capacitor value is 0.1 μF. The AVCC resistor should be placed between PVCC and AVCC pins. The recommended AVCC resistor value is 10 Ω.

VOUT Filter (CVOUT, RVOUT)

The VOUT pin is the input of the internal VCC regulator and also is the input of the output voltage sensing. To minimize noise at the VOUT pin, a 1-μF capacitor must be placed at the VOUT pin in most cases. If multiple output capacitors are used, one of them can be placed at the VOUT pin as CVOUT. The VOUT capacitor must be a high-quality, low-ESR, ceramic capacitor and must be placed close to the device. A resistor can be added at the VOUT pin (RVOUT) to form a RC filter (see Figure 19). In this case, the maximum resistor value should be less than or equal to 2 Ω.

Input Capacitor

The input capacitors reduce the input voltage ripple. Assuming high-quality ceramic capacitors are used for the input capacitors, the maximum input voltage ripple can be calculated by using Equation 39.

Equation 39. LM5150-Q1 eq_49_SNVSAP6.gif

The required input capacitor value is a function of the impedance of the source power supply. More input capacitors are required if the impedance of the source power supply is not low enough. In the example, three 10-µF ceramic capacitors are used.

MOSFET Selection

The MOSFET gate driver of the LM5150-Q1 is powered by the internal 5-V VCC regulator. The MOSFET driven by the LM5150-Q1 must have a logic-level gate threshold with its on-resistance specified at 4.5 V or lower and must be rated to handle the maximum output voltage plus any switch node ringing. The maximum gate charge is limited by the 75-mA PVCC sourcing current limit, and is calculated as follows:

Equation 40. LM5150-Q1 eq_50_SNVSAP6.gif

A leadless package is preferred for high switching-frequency designs. The MOSFET gate capacitance should be small enough so that the gate voltage is fully discharged during the off-time.

Diode Selection

A Schottky is the preferred type for D1 diode due to its low forward voltage drop and small reverse recovery charge. Low reverse leakage current is important parameter when selecting the Schottky diode. The diode must be rated to handle the maximum output voltage plus any switching node ringing. Also, it must be able to handle the average output current. To prevent chatter between wake-up and standby, the forward voltage drop of the D1 diode must be less than 0.95 V at full load.

Efficiency Estimation

The total loss of the boost converter (PTOTAL) can be expressed as the sum of the losses in the LM5150-Q1 (PIC), MOSFET power losses (PQ), diode power losses (PD), inductor power losses (PL), and the loss in the sense resistor (PRS).

Equation 41. LM5150-Q1 eq_51_SNVSAP6.gif

PIC can be separated into gate driving loss (PG) and the losses caused by quiescent current (PIQ).

Equation 42. LM5150-Q1 eq_52_SNVSAP6.gif

Each power loss is approximately calculated as follows:

Equation 43. LM5150-Q1 eq_53_SNVSAP6.gif
Equation 44. LM5150-Q1 eq_54_SNVSAP6.gif

IVIN and IVOUT values in each mode can be found in the supply current section of the Electrical Characteristics table.

PQ can be separated into switching loss (PQ(SW)) and conduction loss (PQ(COND)).

Equation 45. LM5150-Q1 eq_55_SNVSAP6.gif

Each power loss is approximately calculated as follows:

Equation 46. LM5150-Q1 eq_56_SNVSAP6.gif

tR and tF are the rise and fall times of the low-side N-channel MOSFET device. ISUPPLY is the input supply current of the boost converter.

Equation 47. LM5150-Q1 eq_57_SNVSAP6.gif

RDS(ON) is the on-resistance of the MOSFET and is specified in the MOSFET data sheet. Consider the RDS(ON) increase due to self-heating.

PD can be separated into diode conduction loss (PVF) and reverse recovery loss (PRR).

Equation 48. LM5150-Q1 eq_58_SNVSAP6.gif

Each power loss is approximately calculated as follows:

Equation 49. LM5150-Q1 eq_59_SNVSAP6.gif
Equation 50. LM5150-Q1 eq_60_SNVSAP6.gif

QRR is the reverse recovery charge of the diode and is specified in the diode datasheet. Reverse recovery characteristics of the diode strongly affect efficiency, especially when the output voltage is high.

PL is the sum of DCR loss (PDCR) and AC core loss (PAC). DCR is the DC resistance of inductor which is mentioned in the inductor data sheet.

Equation 51. LM5150-Q1 eq_61_SNVSAP6.gif

Each power loss is approximately calculated as follows:

Equation 52. LM5150-Q1 eq_62_SNVSAP6.gif
Equation 53. LM5150-Q1 eq_63_SNVSAP6.gif
Equation 54. LM5150-Q1 eq_64_SNVSAP6.gif

∆I is the peak-to-peak inductor current ripple. K, α, and β are core dependent factors which can be provided by the inductor manufacturer.

PRS is calculated as follows:

Equation 55. LM5150-Q1 eq_65_SNVSAP6.gif

Efficiency of the power converter can be estimated as follows:

Equation 56. LM5150-Q1 eq_66_SNVSAP6.gif

Application Curves

LM5150-Q1 Datasheet_figure 21.png
Figure 20. Automatic Wake-Up
LM5150-Q1 Datasheet_figure 22.png
Figure 21. Load Transient (3 A to 1.5 A, 0.1 V/DIV)

System Examples

Lower Standby Threshold in SS Configuration

By connecting the VIN pin to the VOUT pin, the current limit threshold at the current limit comparator input (VCL) is set to 1.2 V. In SS configuration, the VOUT standby threshold is ignored. The device goes into the standby mode when VOUT > VIN standby threshold.

LM5150-Q1 LM5150-Q1-typical-application-04-snvsap6.gif Figure 22. Lower Standby Threshold in SS Configuration

Dithering Using Dither Enabled Device

Dithering is achieved by connecting DITH output to the RT pin through a resistor.

LM5150-Q1 Fig23N.gif Figure 23. Dithering Using Dither Enabled Device LM5141

Clock Synchronization With LM5140

Clock synchronization can be achieved by connecting LM5140's SYNCOUT to SYNC.

LM5150-Q1 Fig24N.gif Figure 24. Clock Synchronization With LM5140

Dynamic Frequency Change

Switching frequency can be changed dynamically during operation by changing the RT resistor.

LM5150-Q1 Fig25N.gif Figure 25. Dynamic Frequency Change

Dithering Using an External Clock

If a low-frequency clock is available, dithering can be achieved by injecting a ramp signal into RT.

LM5150-Q1 Fig26N.gif Figure 26. Dithering Using an External Clock