SNVSAP6 September 2017 LM5150-Q1
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The LM5150-Q1 is a non-synchronous boost controller. The following design procedure can be used to select the external components for the LM5150-Q1. Alternately, the WEBENCH® software may be used to generate complete designs. The WEBENCH software uses an iterative design procedure and accesses comprehensive data bases of components when generating a design. This section presents a simplified discussion of the design process.
The STATUS pin can be used to control an external bypass switch, which turns on when the boost is in standby mode, or to control an external disconnection switch that turns off when the boost is in standby mode. In Figure 17, a P-channel MOSFET is used to connect the boost supply input to the load directly when the boost is in standby mode. This bypass switch can be turned on slowly, but it must be turned off fast after the STATUS pin is pulled up by the wake-up event. The STATUS pin is rated to the absolute maximum 65 V.
In Figure 18, a P-channel MOSFET is used to disconnect the boost supply output from the battery when boost is not required. This disconnection switch can be turned off slowly, but it must be turned on fast after the STATUS pin is pulled up by the wake-up event.
The open-loop transfer function of a boost regulator is defined as the product of modulator transfer function and feedback transfer function.
The modulator transfer function of a current mode boost regulator including a power stage with an embedded current loop can be simplified as a one load pole (F_{LP}), one ESR zero (F_{Z_ESR}), and one Right Half Plane (RHP) zero (F_{RHP}) system, which can be explained as follows.
Modulator transfer function is defined as follows:
where
R_{ESR} is the equivalent series resistance (ESR) of the output capacitor which is specified in the capacitor datasheet.
R_{COMP}, C_{COMP} and C_{HF} (see Figure 19) configure the error amplifier gain and phase characteristics to produce a stable voltage loop with fast response. This compensation network creates a dominant pole at low frequency (F_{DP_EA}), a mid-band zero (F_{Z_EA}), and a high frequency pole (F_{P_EA}).
The feedback transfer function is defined as follows:
where
R_{O} (≈ 10 MΩ) is the output resistance of the error amplifier and Gm (≈ 2 mA/V) is the transconductance of the error amplifier.
Assuming F_{LP} is canceled by F_{Z_EA}, F_{RHP} is much higher than crossover frequency (F_{CROSS}), and F_{Z_ESR} is either canceled by F_{P_EA} or F_{Z_ESR} is much higher than F_{CROSS}, the open-loop transfer function can be simplified as follows:
Because |T(s)|=1 at the crossover frequency, the crossover frequency can be simply estimated using those assumptions.
The LM5150-Q1 requires a minimum number of external components to work. Figure 19 includes all optional components as an example.
Table 6 lists the design parameters for Figure 19.
DESIGN PARAMETER | VALUE |
---|---|
Target Application | Start-stop |
Minimum Input Supply Voltage (V_{SUPPLY(MIN)}) | 2.5 V |
Target Output Voltage (V_{LOAD}) | 8.5 V |
Maximum Load Current (I_{LOAD}) | 2.94 A (≈ 25 Watt) |
Switching Frequency (F_{SW}) | 440 kHz |
D1 Diode Forward Voltage Drop | 0.7 V |
Maximum Inductor Current Ripple Ratio (RR) | 0.6 (= 60%) |
Estimated Full Load Efficiency (Eff) | 0.8 (= 80%) |
Current Limit Margin (M_{CL}) | 1.2 (= 120%) |
F_{LP} over F_{CROSS} (K1) | 0.15 (F_{LP} = 0.15 × F_{CROSS}) |
F_{Z_EA} over F_{LP} (K2) | 3 (F_{Z_EA} = 3 × F_{LP}) |
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Select the value of R_{SET}, referring to Table 1. 9.53 kΩ is chosen to target 8.5 V in SS configuration. In general, about 5% to approximately 10% output undershoot should be considered when selecting the VOUT regulation target.
The value of R_{T} for 440-kHz switching frequency is calculated as follows:
A standard value of 49.9 kΩ is chosen for RT.
In general, higher frequency boost converters are smaller and faster, but they also have higher switching losses and lower efficiency.
When selecting the inductor, consider three key parameters: inductor current ripple ratio (RR), falling slope of the inductor current, and RHP zero frequency (F_{RHP}).
Inductor current ripple ratio is selected to have a balance between core loss and copper loss. The falling slope of the inductor current must be low enough to prevent sub-harmonic oscillation at high duty cycle (additional R_{SL} resistor is required if not). Higher F_{RHP} (= lower inductance) allows a higher crossover frequency and is always preferred when using a smaller value output capacitor.
The inductance value can be selected to set the inductor current ripple between 30% and 70% of the average inductor current as a good compromise between RR, F_{RHP} and inductor falling slope. In this example, 60% ripple ratio (RR = 0.6) is selected as the maximum inductor current ripple ratio (the inductor current ripple ratio is the biggest when D = 0.33). The target inductance value is calculated as follows:
If the target inductance is smaller than the value calculated using Equation 21, consider adding the slope compensation resistor (R_{SL}), as mentioned in the Slope Compensation Ramp (RSL) section, or select a smaller RR and recalculate the inductance using Equation 20.
A standard value of 1.5 µH is chosen for L_{M}. The required inductor saturation current rating is estimated after selecting R_{S} and R_{SL}.
Based on the assumptions that 20% of current limit margin (M_{CL} = 1.2), 80% estimated efficiency (Eff = 0.8) at full load and no R_{SL} populated, R_{S} is calculated using Equation 22 and Equation 23.
Substitute F_{SW_RT} for F_{SYNC} if the clock synchronization is not used.
A standard value of 7 mΩ is chosen for R_{S}. A low-ESL resistor is recommended to minimize the error caused by the ESL.
The minimum inductance value which can prevent sub-harmonic oscillation without R_{SL} is calculated using Equation 24. If the selected inductance value is less than the minimum inductance calculated using Equation 24, add a slope compensation resistor (R_{SL}) externally.
1.2 is the recommended margin to cover non-ideal factors.
If needed, use Equation 25 to find the R_{SL} value which matches the typical amount of slope compensation.
In this example, R_{SL} is not populated because the selected inductance value, 1.5 µH, is greater than the minimum required inductance from Equation 24.
After selecting R_{S} and R_{SL}, the peak inductor current at current limit (I_{PEAK-CL}) can be calculated. Setting the inductor saturation current rating higher than the I_{PEAK-CL} is recommended.
T_{D} is the typical propagation delay of current limit.
There are a few ways to select the proper value of output capacitor (C_{OUT}). The output capacitor value can be selected based on output voltage ripple, output overshoot or undershoot due to load transient. In this example, C_{OUT} is selected based on output undershoot because the waking up performance is similar with no-load to full-load transient performance.
The output undershoot becomes smaller by increasing F_{CROSS} or by decreasing F_{LP}: a smaller C_{OUT} is allowed by increasing F_{CROSS} or by decreasing F_{LP}.
To increase F_{CROSS}, F_{SW} and F_{RHP} must be increased because the maximum F_{CROSS} is, in general, limited at 1/10 of F_{RHP} at V_{SUPPLY(MIN)} or 1/10 of F_{SW} whichever is lower.
F_{RHP} is calculated using Equation 28.
F_{CROSS} is selected at 1/10 of F_{RHP} or 1/10 of F_{SW}, whichever is lower.
In this example, 2.27 kHz is selected as a target F_{CROSS} and F_{LP} is selected to be 340 Hz (K1 = 0.15).
In general, there is about 5% or less undershoot with F_{LP} = 0.1 × F_{CROSS} (K1 = 0.1) and 10% or less undershoot with F_{LP} = 0.2 × F_{CROSS} (K1 = 0.2) during 0% to 100% load transient. The recommended K1 factor range is from 0.02 to 0.2.
F_{LP} is calculated using Equation 31.
The minimum required output capacitance value is calculated using Equation 32.
The maximum output ripple current is calculated at the minimum input supply voltage as follows:
The ripple current rating of the output capacitors must be enough to handle the output ripple current. By using multiple output capacitors, the ripple current can be split. In practice, ceramic capacitors are placed closer to the diode and the MOSFET than the bulk aluminum capacitors in order to absorb the majority of the ripple current.
In this example, three 100-µF capacitors are placed in parallel to ensure ripple current capability. If high-ESR capacitors are used for the output capacitor, additional 10-µF ceramic capacitors can be placed close to the switching components to minimize switching noise.
Based on Equation 18, C_{COMP} is calculated as follows:
By selecting C_{COMP} following Equation 34, the typical phase margin is set to 90⁰ and the loop response is overdamped. In this example, F_{Z_EA} is placed at 3 times higher frequency than F_{LP} to have lower phase margin but faster settling time (K2 = 3, target F_{Z_EA} is 1.02 kHz). Recommended range of F_{Z_EA} is from 1 × F_{LP} to 4 × F_{LP} (1 ≤ K2 ≤ 4). Practical crossover frequency will vary with K2 with a range of 0.5 × F_{CROSS} to 1.0 × F_{CROSS}.
A standard value of 33 nF is chosen for C_{COMP}.
R_{COMP} is selected to set the error amplifier zero at 1.02 kHz.
A standard value of 4.64 kΩ is chosen for R_{COMP}.
C_{HF} is usually used to create a pole at high frequency (F_{P_EA}) to cancel F_{Z_ESR}. By using a small ESR capacitor which can place F_{Z_ESR} greater than 10 × F_{CROSS}, the output capacitor ESR would not affect the loop stability. The maximum ESR which does not affect the loop response is calculated using Equation 38.
The PVCC capacitor supplies the peak transient current to the LO driver. The value of PVCC capacitor (C_{PVCC}) must be 4.7 μF or higher and must be a high-quality, low-ESR, ceramic capacitor. C_{PVCC} must be placed close to the PVCC pin and the PGND pin. A value of 4.7 μF is selected for this design example. The AVCC capacitor must be placed close to the device. The recommended AVCC capacitor value is 0.1 μF. The AVCC resistor should be placed between PVCC and AVCC pins. The recommended AVCC resistor value is 10 Ω.
The VOUT pin is the input of the internal VCC regulator and also is the input of the output voltage sensing. To minimize noise at the VOUT pin, a 1-μF capacitor must be placed at the VOUT pin in most cases. If multiple output capacitors are used, one of them can be placed at the VOUT pin as C_{VOUT}. The VOUT capacitor must be a high-quality, low-ESR, ceramic capacitor and must be placed close to the device. A resistor can be added at the VOUT pin (R_{VOUT}) to form a RC filter (see Figure 19). In this case, the maximum resistor value should be less than or equal to 2 Ω.
The input capacitors reduce the input voltage ripple. Assuming high-quality ceramic capacitors are used for the input capacitors, the maximum input voltage ripple can be calculated by using Equation 39.
The required input capacitor value is a function of the impedance of the source power supply. More input capacitors are required if the impedance of the source power supply is not low enough. In the example, three 10-µF ceramic capacitors are used.
The MOSFET gate driver of the LM5150-Q1 is powered by the internal 5-V VCC regulator. The MOSFET driven by the LM5150-Q1 must have a logic-level gate threshold with its on-resistance specified at 4.5 V or lower and must be rated to handle the maximum output voltage plus any switch node ringing. The maximum gate charge is limited by the 75-mA PVCC sourcing current limit, and is calculated as follows:
A leadless package is preferred for high switching-frequency designs. The MOSFET gate capacitance should be small enough so that the gate voltage is fully discharged during the off-time.
A Schottky is the preferred type for D1 diode due to its low forward voltage drop and small reverse recovery charge. Low reverse leakage current is important parameter when selecting the Schottky diode. The diode must be rated to handle the maximum output voltage plus any switching node ringing. Also, it must be able to handle the average output current. To prevent chatter between wake-up and standby, the forward voltage drop of the D1 diode must be less than 0.95 V at full load.
The total loss of the boost converter (P_{TOTAL}) can be expressed as the sum of the losses in the LM5150-Q1 (P_{IC}), MOSFET power losses (P_{Q}), diode power losses (P_{D}), inductor power losses (P_{L}), and the loss in the sense resistor (P_{RS}).
P_{IC} can be separated into gate driving loss (P_{G}) and the losses caused by quiescent current (P_{IQ}).
Each power loss is approximately calculated as follows:
I_{VIN} and I_{VOUT} values in each mode can be found in the supply current section of the Electrical Characteristics table.
P_{Q} can be separated into switching loss (P_{Q(SW)}) and conduction loss (P_{Q(COND)}).
Each power loss is approximately calculated as follows:
t_{R} and t_{F} are the rise and fall times of the low-side N-channel MOSFET device. I_{SUPPLY} is the input supply current of the boost converter.
R_{DS(ON)} is the on-resistance of the MOSFET and is specified in the MOSFET data sheet. Consider the R_{DS(ON)} increase due to self-heating.
P_{D} can be separated into diode conduction loss (P_{VF}) and reverse recovery loss (P_{RR}).
Each power loss is approximately calculated as follows:
Q_{RR} is the reverse recovery charge of the diode and is specified in the diode datasheet. Reverse recovery characteristics of the diode strongly affect efficiency, especially when the output voltage is high.
P_{L} is the sum of DCR loss (P_{DCR}) and AC core loss (P_{AC}). DCR is the DC resistance of inductor which is mentioned in the inductor data sheet.
Each power loss is approximately calculated as follows:
∆I is the peak-to-peak inductor current ripple. K, α, and β are core dependent factors which can be provided by the inductor manufacturer.
P_{RS} is calculated as follows:
Efficiency of the power converter can be estimated as follows:
By connecting the VIN pin to the VOUT pin, the current limit threshold at the current limit comparator input (V_{CL}) is set to 1.2 V. In SS configuration, the VOUT standby threshold is ignored. The device goes into the standby mode when VOUT > VIN standby threshold.
Dithering is achieved by connecting DITH output to the RT pin through a resistor.
Clock synchronization can be achieved by connecting LM5140's SYNCOUT to SYNC.
Switching frequency can be changed dynamically during operation by changing the RT resistor.
If a low-frequency clock is available, dithering can be achieved by injecting a ramp signal into RT.