SNVSAP6 September   2017 LM5150-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable (EN Pin)
      2. 7.3.2  High Voltage VCC Regulator (PVCC, AVCC Pin)
      3. 7.3.3  Power-On Voltage Selection (VSET Pin)
      4. 7.3.4  Switching Frequency (RT Pin)
      5. 7.3.5  Clock Synchronization (SYNC Pin in SS Configuration)
      6. 7.3.6  Current Sense, Slope Compensation, and PWM (CS Pin)
      7. 7.3.7  Current Limit (CS Pin)
      8. 7.3.8  Feedback and Error Amplifier (COMP Pin)
      9. 7.3.9  Automatic Wake-Up and Standby
      10. 7.3.10 Boost Status Indicator (STATUS Pin)
      11. 7.3.11 Maximum Duty Cycle Limit, Minimum Input Supply Voltage
      12. 7.3.12 MOSFET Driver (LO Pin)
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Wake-Up Mode
        1. 7.4.3.1 Start-Stop Configuration (SS Configuration)
        2. 7.4.3.2 Emergency-Call Configuration (EC Configuration)
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bypass Switch / Disconnection Switch Control
      2. 8.1.2 Loop Response
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  RSET Resistor
        3. 8.2.2.3  RT Resistor
        4. 8.2.2.4  Inductor Selection (LM)
        5. 8.2.2.5  Current Sense (RS)
        6. 8.2.2.6  Slope Compensation Ramp (RSL)
        7. 8.2.2.7  Output Capacitor (COUT)
        8. 8.2.2.8  Loop Compensation Component Selection and Maximum ESR
        9. 8.2.2.9  PVCC Capacitor, AVCC Capacitor, and AVCC Resistor
        10. 8.2.2.10 VOUT Filter (CVOUT, RVOUT)
        11. 8.2.2.11 Input Capacitor
        12. 8.2.2.12 MOSFET Selection
        13. 8.2.2.13 Diode Selection
        14. 8.2.2.14 Efficiency Estimation
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Lower Standby Threshold in SS Configuration
      2. 8.3.2 Dithering Using Dither Enabled Device
      3. 8.3.3 Clock Synchronization With LM5140
      4. 8.3.4 Dynamic Frequency Change
      5. 8.3.5 Dithering Using an External Clock
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RUM|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description

Overview

The LM5150-Q1 device is a wide input range automotive boost controller designed for automotive start-stop or emergency-call applications. The device can maintain the output voltage from a vehicle battery during automotive cranking or from a back-up battery during the loss of vehicle battery. The wide input range of the device covers automotive load dump transient. The control method is based upon peak current mode control.

To extend the battery life time, the LM5150-Q1 features a low IQ standby mode with automatic wake-up and standby control. The device stays in the low IQ standby mode when the boost operation is not required, and automatically enters the wake-up mode when the output voltage drops below the preset wake-up threshold. High value feedback resistors are included inside the device to minimize leakage current in the low IQ standby mode.

The LM5150-Q1 operates in one of two selectable configurations when waking up. In Start-Stop configuration (SS configuration), the device runs at a fixed switching frequency without any pulse skipping until entering into the standby mode, which helps to have a fixed EMI spectrum. In Emergency-Call configuration (EC configuration), the device will skip pulses as it automatically alternates between low IQ standby mode and wake-up mode to extend the battery life in light load conditions.

The LM5150-Q1 switching frequency is programmable from 220 kHz to 2.3 MHz. Fast switching (≥ 2.2-MHz) minimizes AM band interference and allows for a small solution size and fast transient response. A single resistor at the VSET pin programs the target output regulation voltage as well as the configuration. This eliminates the need for an external feedback resistor divider which enables low IQ operation. The device also features clock synchronization in the SS configuration, low quiescent current in shutdown mode, a boost status indicator, adjustable cycle-by-cycle current will limit, and thermal shutdown protection.

Functional Block Diagram

LM5150-Q1 LM5150-Q1-functional-block-diagram-snvsap6_v3.gif

Feature Description

Enable (EN Pin)

When the EN pin voltage is less than 1 V, the LM5150-Q1 is in shutdown mode with all other functions disabled. To turn on the internal VCC regulator and begin start-up sequence, the EN pin voltage must be greater than 2 V. If the EN pin is controlled by user input, it is recommended to supply a voltage greater than 3 V at the EN pin. If the EN pin is not controlled by user input, connect the EN pin to the VOUT pin directly. See Device Functional Modes for more detailed information.

High Voltage VCC Regulator (PVCC, AVCC Pin)

The LM5150-Q1 contains an internal high voltage VCC regulator. The VCC regulator turns on when the EN pin voltage is greater than 2 V. The VCC regulator is sourced from the VOUT pin and provides 5 V (typical) bias supply for the N-channel MOSFET driver and other internal circuits.

The VCC regulator sources current into the capacitor connected to the PVCC pin with a minimum of 75-mA capability when the LM5150-Q1 is in the wake-up mode and during the device configuration period. The maximum sourcing capability is decreased to 17 mA in standby mode. The recommended PVCC capacitor is 4.7 µF to 10 µF. In normal operation, the PVCC pin voltage is either 5 V or VVOUT + 0.3 V, whichever is lower.

The AVCC pin is the analog bias supply input of the LM5150-Q1. The recommended AVCC capacitor is 0.1-μF. Connect to the PVCC pin through 10-Ω resistor.

Power-On Voltage Selection (VSET Pin)

During initial power on, the VOUT regulation target and the configuration are configured by a resistor connected between the VSET and the AGND pins. The configuration starts when the EN pin voltage is greater than 2 V and the AVCC voltage crosses the AVCC UVLO threshold, and requires typically 50 µs to finish. To reset and reconfigure, EN should be toggled below 1 V or AVCC/VOUT must be fully discharged.

LM5150-Q1 LM5150-Q1-shutdown-configuration-snvsap6.gif Figure 9. Power-On Voltage Selection

The VOUT regulation target can be programmed to 6.8 V, 7.5 V, 8.5 V, or 10.5 V with the appropriate resistor with 5% tolerance. The configuration can be selected as either SS or EC configuration. The LM5150-Q1 will not switch during the 50-µs configuration time.

Table 1. VSET Resistors(1)

CONFIGURATION EMERGENCY-CALL START-STOP
VOUT regulation target 6.8 V 7.5 V 8.5 V 10.5 V 6.8 V 7.5 V 8.5 V 10.5 V
RSET [Ω] 90.9k 71.5k 54.9k 41.2k 29.4k 19.1k 9.53k Ground
If other output regulation targets are required, contact the sales office/distributors for availability.

Switching Frequency (RT Pin)

The switching frequency of the LM5150-Q1 is set by a single RT resistor connected between the RT and the AGND pins. The resistor value to set the switching frequency (FSW) is calculated using Equation 1.

Equation 1. LM5150-Q1 LM5150-Q1-equation-01-snvsap6.gif

The RT pin is regulated to 1.2 V by the internal RT regulator during wake-up.

Clock Synchronization (SYNC Pin in SS Configuration)

In SS configuration, the switching frequency of the LM5150-Q1 can be synchronized to an external clock by directly applying a pulse signal to the SYNC pin. The internal clock of the LM5150-Q1 is synchronized at the rising edge of the external clock. The device ignores the rising edge input during forced off-time.

The external synchronization pulse must be greater than the 2.4 V in the high logic state and must be less than 0.4 V in the low logic state. The duty cycle of the external synchronization pulse is not limited, but the minimum pulse width should be greater than 100 ns. Because the maximum duty cycle limit and the peak current limit threshold are affected by synchronizing the switching frequency to an external synchronization pulse, take extra care when using the clock synchronization function. See the Maximum Duty Cycle Limit, Minimum Input Supply Voltage and Current Limit (CS Pin) section for more detailed information.

If the boost converter’s minimum input supply voltage is greater than ¼ of the VOUT regulation target (VVOUT-REG), the frequency of the external synchronization pulse (FSYNC) should be within +15% and –15% of the typical free-running switching frequency (FSW(TYPICAL))

Equation 2. LM5150-Q1 eq_2_SNVSAP6.gif

In this range, a maximum 1:4 (VSUPPLY:VLOAD) step-up ratio is allowed.

A higher step-up ratio can be achieved by supplying a lower frequency synchronization pulse. 1:5 step-up ratio can be achieved by selecting FSYNC within –25% and –15% of the FSW_RT(TYPICAL).

Equation 3. LM5150-Q1 eq_3_SNVSAP6.gif

In this range, a maximum 1:5 (VSUPPLY:VLOAD) step-up ratio is allowed.

Current Sense, Slope Compensation, and PWM (CS Pin)

The LM5150-Q1 features low-side current sense amplifier with a gain of 10, and provides an internal slope compensation ramp to prevent sub-harmonic oscillation at high duty cycle. The device generates the slope compensation ramp using a sawtooth current source with a slope of 30 µA × FSW (typical). This current flows through an internal 2-kΩ resistor and out of the CS pin. The slope compensation ramp is determined by the RT resistor and is 60 mV × FSW (typical) at the input of the current sense amplifier and 600 mV × FSW (typical) at the output of the current sense amplifier. The slope compensation ramp can be increased by adding an external slope resistor (RSL) between the sense resistor (RS) and the CS pin, but take extra care when using the RSL, because the peak current limit is affected by adding RSL. See Current Limit (CS Pin) for more detailed information.

LM5150-Q1 LM5150-Q1-typical-application-01-snvsap6.gif Figure 10. Current Sensing and Slope Compensation

According to peak current mode control theory, the slope of the compensation ramp must be greater than half of the sensed inductor current falling slope to prevent sub-harmonic oscillation at high duty cycle. Therefore, the minimum amount of slope compensation should satisfy the following inequality.

Equation 4. LM5150-Q1 eq_4_SNVSAP6.gif

VF is a forward voltage drop of D1, the external diode. 1.2 is recommended as a margin to cover non-ideal factors.

If required, RSL can be added to increase the slope of the compensation ramp from half to 82% of the slope of the sensed inductor current during the falling slope. The typical RSL value is calculated using Equation 5. The maximum RSL value is 1 kΩ

Equation 5. LM5150-Q1 eq_5_SNVSAP6.gif

The PWM comparator in Figure 10 compares the sum of sensed inductor current, slope compensation ramp and a 0.3-V (typical) internal COMP-to-PWM offset with the COMP pin voltage (VCOMP), and terminates the present cycle if the sum is greater than VCOMP.

Current Limit (CS Pin)

The LM5150-Q1 features cycle-by-cycle peak current limit without sub-harmonic oscillation at high duty cycle. If the sum of the sensed inductor current and the slope compensation ramp exceeds the current limit threshold at the current limit comparator input (VCL), the current limit comparator immediately terminates the present cycle. To minimize the peak current limit variation due to changes in either the supply voltage or the output voltage, the device features a variable current limit threshold which is calculated using Equation 6.

Equation 6. LM5150-Q1 eq_6_SNVSAP6.gif

Cycle-by-cycle peak inductor current limit (IPEAK-CL) in steady state calculated as follows:

Equation 7. LM5150-Q1 eq_7_SNVSAP6.gif
Equation 8. LM5150-Q1 eq_8_SNVSAP6.gif

FSYNC is included in the equation because the peak amplitude of the slope compensation varies with the frequency of the external synchronization clock. Substitute FSW_RT for FSYNC if clock synchronization is not used.

Boost converters have a natural pass-through path from the supply to the load through the high-side power diode (D1). Due to this path, boost converters cannot provide current limit protection when the output voltage is close to or less than the input supply voltage.

A small external RC filter (RF, CF) at the CS pin is required to overcome the leading edge spike of the current sense signal. Select an RF value which is greater than 30 Ω and a CF value which is greater than 1 nF. Due to the effect of the filter, the peak current limit is not valid when the on-time is less than 2 × RF × CF.

Feedback and Error Amplifier (COMP Pin)

The LM5150-Q1 includes internal feedback resistors which are set based on the VSET pin resistor selection. These feedback resistors are disconnected from the VOUT pin in the standby mode to minimize quiescent current. The feedback resistor divider is connected to an internal transconductance error amplifier which features high output resistance (RO = 10 MΩ) and wide bandwidth (BW = 3 MHz). The internal transconductance error amplifier sources current which is proportional to the difference between the feedback resistor divider voltage and the internal reference. The output of the error amplifier is connected to the COMP pin, allowing the use of a Type 2 loop compensation network.

RCOMP, CCOMP and optional CHF loop compensation components configure the error amplifier gain and phase characteristics to achieve a stable loop response. This compensation network creates a pole at very low frequency (FDP), a mid-band zero (FZ_EA) and a high frequency pole (FP_EA). See Loop Compensation Component Selection and Maximum ESR for more detailed information.

Automatic Wake-Up and Standby

The LM5150-Q1 wakes up when VVOUT drops below the VOUT wake-up threshold. The device goes into standby when VVOUT rises above the VOUT standby threshold in EC or SS configuration or when VVIN rises above the VIN standby threshold in SS configuration. The VOUT wake-up threshold is typically 3% higher than the VOUT regulation target. The STATUS output is released in 3 µs (with 50-kΩ pullup resistor to 5 V) after the wake-up event. The LO driver is enabled 6 µs after the STATUS output starts rising.

LM5150-Q1 Fig11N.gif Figure 11. Automatic Wake-Up and Standby Control

In SS configuration, the VOUT standby threshold is typically 24% higher than the VOUT regulation target. The VIN standby threshold is typically 1 V higher than the VOUT wake-up threshold in SS configuration. To prevent chatter, the forward voltage drop of diode D1 must be less than 0.95 V. See Figure 15.

LM5150-Q1 Fig12N.gif Figure 12. Automatic Wake-Up and Standby Operation in the SS Configuration
(With Fast VSUPPLY Fall and Slow Switching)
LM5150-Q1 Fig13N.gif Figure 13. Automatic Wake-Up and Standby Operation in the SS Configuration
(With Slow VSUPPLY Fall and Fast Switching)

In EC configuration, the VOUT standby threshold is typically 6% higher than the VOUT regulation target. Because of the minimum duty cycle limit (see Emergency-Call Configuration (EC Configuration)), the LM5150-Q1 alternates between the wake-up and the low IQ standby modes at medium or light load. See Figure 16.

LM5150-Q1 Fig14N.gif Figure 14. Automatic Wake-Up and Standby Operation in EC Configuration

To minimize output undershoot when waking up, the LM5150-Q1 boosts the VOUT regulation target during the first 128 cycles after the wake-up event. The regulation target becomes 3% higher than the original regulation target for 64 cycles, 2% higher for the next 32 cycles and 1% higher for the final 32 cycles. The VOUT pin voltage may rise up above the VOUT standby threshold even if switching stops at the VOUT standby threshold because the energy stored in the inductor transfers to the output capacitor when switching stops. See Device Functional Modes for more information about the automatic wake-up and standby operation.

Boost Status Indicator (STATUS Pin)

STATUS is an open-drain output and requires a pullup resistor between 5 kΩ and 100 kΩ. The pin is pulled up after VVOUT falls below the VOUT wake-up threshold, and is toggled to a low logic state when VVIN rises above the VIN standby threshold in SS configuration or when VVOUT rises above the VOUT status off-threshold in EC configuration. The pin is also pulled to ground when EN < 1 V and VOUT is greater than about 2 V, when AVCC < VVCC-UVLO-FALLING or during thermal shutdown.

Maximum Duty Cycle Limit, Minimum Input Supply Voltage

When designing a boost converter, the maximum duty cycle should be reviewed at the minimum supply voltage. The minimum input supply voltage which can achieve the target output voltage is estimated from Equation 9.

Equation 9. LM5150-Q1 eq_10_SNVSAP6.gif

ISUPPLY(MAX) is the maximum input current. RDCR is the DC resistance of the inductor. RDS(ON) is the on-resistance of the MOSFET. Substitute FSW_RT for FSYNC if the clock synchronization is not used. The minimum input supply voltage can be decreased by supplying FSYNC which is less than FSW_RT.

This maximum duty cycle limit (DMAX) is 87% (typical), but may fall down below 80% if the external synchronization clock frequency is higher than 0.85 × FSW (TYPICAL). Select an FSYNC which is within –25% and –15% of the FSW (TYPICAL) if 1:5 step-up ratio is required with clock synchronization. The minimum input supply voltage can be further decreased by supplying a lower frequency external synchronization clock. See Clock Synchronization (SYNC Pin in SS Configuration) for more information.

MOSFET Driver (LO Pin)

The LM5150-Q1 provides an N-channel MOSFET driver which can source or sink a peak current of 1.5 A. The driver is powered by the 5-V VCC regulator and is enabled when the EN pin voltage is greater than 2 V and the AVCC pin voltage is greater than the AVCC UVLO threshold.

Thermal Shutdown

Internal thermal shutdown is provided to protect the LM5150-Q1 if the junction temperature exceeds 175°C (typical). When thermal shutdown is activated, the device is forced into a low power thermal shutdown state with the MOSFET driver and the VCC regulator disabled. After the junction temperature is reduced (typical hysteresis is 15⁰C), the device is re-enabled.

Device Functional Modes

Shutdown Mode

If the EN pin voltage is below 1 V, the LM5150-Q1 is in shutdown mode with all functions disabled except EN. In shutdown mode, the device reduces the VOUT pin current consumption to below 5.25 µA (typical) and the STATUS pin is pulled to ground. The device can be enabled by raising the EN pin above 2 V and operates in either the standby mode or the wake-up mode if VAVCC is greater than the AVCC UVLO threshold.

Table 2. State of Each Pin in Shutdown Mode

STATUS SYNC RT COMP EN VOUT PVCC/AVCC LO CS VIN VSET
Grounded Disabled Disabled Disabled Enabled IQ ≤ 5 µA Disabled Grounded Disabled IQ ≈ 0.1 µA Disabled

Standby Mode

If VOUT is greater than the VOUT standby threshold or VIN is greater than the VIN standby threshold in the SS mode, the LM5150-Q1 enters into standby mode.

In standby mode, most functions are disabled, including the thermal shutdown, to minimize the current consumption. The VOUT wake-up monitor is enabled in standby mode to allow wake-up if the VOUT voltage drops below the VOUT wake-up threshold. The VCC regulator reduces the sourcing capability to 17 mA in standby mode and the AVCC UVLO comparator is disabled.

The VOUT standby threshold fulfills effectively the overvoltage protection (OVP) function.

Table 3. State of Each Pin in Standby Mode

STATUS SYNC RT COMP EN VOUT PVCC/AVCC LO CS VIN VSET
Released or Grounded Disabled Disabled Disabled Enabled IQ ≤ 15 µA. VOUT wake-up monitor enabled Enabled IPVCC capability ≈ 17 mA Grounded Disabled IQ ≈ 0.1 µA Disabled

Wake-Up Mode

The LM5150-Q1 wakes up from standby mode if VOUT drops below the VOUT wake-up threshold. There are two configurations when the device wakes up. One is start-stop configuration (SS configuration) and the other is emergency-call configuration (EC configuration). The configuration is selectable by the VSET resistor (see Table 1).

Start-Stop Configuration (SS Configuration)

LM5150-Q1 LM5150-Q1-typical-application-02-snvsap6.gif Figure 15. Typical Start-Stop Application

The LM5150-Q1 runs at fixed switching frequency without any pulse skipping in SS configuration. The device turns on the LO driver every cycle with TON-MIN until entering into standby mode, which helps to prevent EMI spectrum shifts. Because the MOSFET turns on every cycle, the boost converter output may be above the regulation target if the required on-time is less than the TON-MIN when the boost supply voltage is close to the VOUT regulation target or the load current is very small. The output voltage will rise above the VOUT regulation target if the one of the inequalities below is true.

Equation 10. LM5150-Q1 eq_11_SNVSAP6.gif
Equation 11. LM5150-Q1 eq_12_SNVSAP6.gif

In SS configuration, the LM5150-Q1 enters into the standby mode if VOUT is greater than the VOUT standby threshold—which is 24% higher than the VOUT regulation target—or if VIN is greater than the VIN standby threshold.

Emergency-Call Configuration (EC Configuration)

LM5150-Q1 LM5150-Q1-typical-application-03-snvsap6.gif Figure 16. Typical Emergency Call Application

The EC configuration achieves high efficiency at light/medium load by alternating between the wake-up and the low IQ standby modes. In EC configuration, the LM5150-Q1 limits the minimum duty cycle programmed by VVOUT and VVIN. The minimum duty cycle limit is calculated using Equation 12.

Equation 12. LM5150-Q1 eq_13_SNVSAP6.gif

Due to this minimum duty cycle limit, the boost converter sources more current than required when the load current is relatively small. As a result, the output voltage increases and eventually crosses the VOUT standby threshold which is typically 6% higher than the VOUT regulation target. The LM5150-Q1 then goes into the low IQ standby mode. The LM5150-Q1 wakes up when VOUT drops below the VOUT wake-up threshold which is typically 3% higher than the VOUT regulation target. The device alternates between these two modes when the inequality below is true.

Equation 13. LM5150-Q1 eq_14_SNVSAP6.gif

Assuming VLOAD = VVOUT = VVOUT-REG and VSUPPLY = VVIN, the skip cycle operation starts when the inequality below is true.

Equation 14. LM5150-Q1 eq_15_SNVSAP6.gif

In EC configuration, the LM5150-Q1 doesn’t generate any pulse if VCOMP is less than the 0.3 V and the required minimum duty cycle limit is zero.

If the peak current limit is triggered before reaching the minimum duty cycle, the device terminates the LO driver output immediately.

If VOUT is greater than the VOUT status-off threshold (typically 12% higher than the VOUT regulation target), the LM5150-Q1 pulls the STATUS pin low.

In EC configuration, light load efficiency is proportional with the inductor current ripple ratio.

Table 4. State of Each Pin in Wake-Up Mode

STATUS SYNC RT COMP EN VOUT PVCC/AVCC LO CS VIN VSET
Released Enabled in SS configuration Enabled Enabled Enabled VOUT standby monitor is enabled. VOUT status-off monitor is enabled in EC configuration. Enabled IPVCC capability ≈ 75 mA PWM Enabled IQ ≈ 30 µA. VIN status-off monitor is enabled in SS configuration Disabled

Table 5. Start-Stop vs Emergency-Call Configuration

CONFIGURATION START-STOP EMERGENCY-CALL
VOUT regulation options 6.8 V, 7.5 V, 8.5 V, 10.5 V
VSET resistor value [Ω] 29.4k, 19.1k, 9.53k, GND 90.9k, 71.5k, 54.9k, 41.2k
Clock Synchronization Yes No, SYNC should be grounded
VOUT wake-up threshold [V] VVOUT-REG × 1.03
VOUT standby threshold [V] VVOUT-REG × 1.24 VVOUT-REG × 1.06
VOUT status-off threshold [V] N/A VVOUT-REG × 1.12
VIN standby threshold [V] VVOUT-REG × 1.03 + 1.0 V N/A
STATUS pin control (Open-drain with pullup resistor) Released by VOUT wake-up
Pulled down by VIN standby
Released by VOUT wake-up
Pulled down by VOUT status-off
At heavy load when VVIN « VVOUT Pulse width modulation (PWM)
At light/no load when VVIN « VVOUT LO turns on at every cycle in wake-up configuration. Skip cycle operation by alternating between wake-up and standby configurations.
Minimum on-time is limited Minimum duty cycle is limited
When VVIN ≈ VVOUT or VVIN ≥ VVOUT LO turns on at every cycle in wake-up configuration. On-time is limited by TON-MIN. VOUT goes out of regulation. Duty cycle can drop to 0%. No pulses if VCOMP < 0.3 V and DMIN ≤ 0%.
Maximum duty-cycle limit Typically 87%