SNVSAP6 September   2017 LM5150-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable (EN Pin)
      2. 7.3.2  High Voltage VCC Regulator (PVCC, AVCC Pin)
      3. 7.3.3  Power-On Voltage Selection (VSET Pin)
      4. 7.3.4  Switching Frequency (RT Pin)
      5. 7.3.5  Clock Synchronization (SYNC Pin in SS Configuration)
      6. 7.3.6  Current Sense, Slope Compensation, and PWM (CS Pin)
      7. 7.3.7  Current Limit (CS Pin)
      8. 7.3.8  Feedback and Error Amplifier (COMP Pin)
      9. 7.3.9  Automatic Wake-Up and Standby
      10. 7.3.10 Boost Status Indicator (STATUS Pin)
      11. 7.3.11 Maximum Duty Cycle Limit, Minimum Input Supply Voltage
      12. 7.3.12 MOSFET Driver (LO Pin)
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Wake-Up Mode
        1. 7.4.3.1 Start-Stop Configuration (SS Configuration)
        2. 7.4.3.2 Emergency-Call Configuration (EC Configuration)
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bypass Switch / Disconnection Switch Control
      2. 8.1.2 Loop Response
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  RSET Resistor
        3. 8.2.2.3  RT Resistor
        4. 8.2.2.4  Inductor Selection (LM)
        5. 8.2.2.5  Current Sense (RS)
        6. 8.2.2.6  Slope Compensation Ramp (RSL)
        7. 8.2.2.7  Output Capacitor (COUT)
        8. 8.2.2.8  Loop Compensation Component Selection and Maximum ESR
        9. 8.2.2.9  PVCC Capacitor, AVCC Capacitor, and AVCC Resistor
        10. 8.2.2.10 VOUT Filter (CVOUT, RVOUT)
        11. 8.2.2.11 Input Capacitor
        12. 8.2.2.12 MOSFET Selection
        13. 8.2.2.13 Diode Selection
        14. 8.2.2.14 Efficiency Estimation
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Lower Standby Threshold in SS Configuration
      2. 8.3.2 Dithering Using Dither Enabled Device
      3. 8.3.3 Clock Synchronization With LM5140
      4. 8.3.4 Dynamic Frequency Change
      5. 8.3.5 Dithering Using an External Clock
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RUM|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout

Layout Guidelines

The performance of switching converters heavily depends on the quality of the PCB layout. The following guidelines will help users design a PCB with the best power conversion performance, thermal performance, and minimize generation of unwanted EMI.

  • Place Q1, D1, and RS first.
  • Place ceramic COUT and make the switching loop (COUT-D1-Q1-RS-COUT) as small as possible.
  • Leave copper area next to D1 for thermal dissipation.
  • Place LM5150-Q1 close to RS.
  • Place CPVCC as close to the device as possible between PVCC and PGND.
  • Connect PGND directly to the center of the sense resistor using a wide and short trace.
  • Connect CS to the center of the sense resistor. Connect through vias if required. Connect filter capacitor between CS pin and exposed pad.
  • Connect AGND directly to the analog ground plain and connect to RSET, RT, and CCOMP.
  • Connect the exposed pad to the analog ground plain and the power ground plain through vias.
  • Connect LO directly to the gate of Q1.
  • Make the switching signal loop (LO-Q1-RS-PGND-LO) as small as possible.
  • Place CVOUT as close to the device as possible.
  • The LM5150-Q1 has an exposed thermal pad to aid power dissipation. Adding several vias under the exposed pad helps conduct heat away from the device. Connect the vias to a large ground plane on the bottom layer.

Layout Example

LM5150-Q1 LM5150-Q1-layout-example-snvsap6.png Figure 27. LM5150-Q1 PCB Layout Example