SNVSAP6 September   2017 LM5150-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable (EN Pin)
      2. 7.3.2  High Voltage VCC Regulator (PVCC, AVCC Pin)
      3. 7.3.3  Power-On Voltage Selection (VSET Pin)
      4. 7.3.4  Switching Frequency (RT Pin)
      5. 7.3.5  Clock Synchronization (SYNC Pin in SS Configuration)
      6. 7.3.6  Current Sense, Slope Compensation, and PWM (CS Pin)
      7. 7.3.7  Current Limit (CS Pin)
      8. 7.3.8  Feedback and Error Amplifier (COMP Pin)
      9. 7.3.9  Automatic Wake-Up and Standby
      10. 7.3.10 Boost Status Indicator (STATUS Pin)
      11. 7.3.11 Maximum Duty Cycle Limit, Minimum Input Supply Voltage
      12. 7.3.12 MOSFET Driver (LO Pin)
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Wake-Up Mode
        1. 7.4.3.1 Start-Stop Configuration (SS Configuration)
        2. 7.4.3.2 Emergency-Call Configuration (EC Configuration)
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bypass Switch / Disconnection Switch Control
      2. 8.1.2 Loop Response
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  RSET Resistor
        3. 8.2.2.3  RT Resistor
        4. 8.2.2.4  Inductor Selection (LM)
        5. 8.2.2.5  Current Sense (RS)
        6. 8.2.2.6  Slope Compensation Ramp (RSL)
        7. 8.2.2.7  Output Capacitor (COUT)
        8. 8.2.2.8  Loop Compensation Component Selection and Maximum ESR
        9. 8.2.2.9  PVCC Capacitor, AVCC Capacitor, and AVCC Resistor
        10. 8.2.2.10 VOUT Filter (CVOUT, RVOUT)
        11. 8.2.2.11 Input Capacitor
        12. 8.2.2.12 MOSFET Selection
        13. 8.2.2.13 Diode Selection
        14. 8.2.2.14 Efficiency Estimation
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Lower Standby Threshold in SS Configuration
      2. 8.3.2 Dithering Using Dither Enabled Device
      3. 8.3.3 Clock Synchronization With LM5140
      4. 8.3.4 Dynamic Frequency Change
      5. 8.3.5 Dithering Using an External Clock
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RUM|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Specifications

Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)(1)
MIN MAX UNIT
Input VIN to AGND -0.3 65 V
VOUT to AGND -0.3 65
EN to AGND -0.3 65
RT to AGND(2) -0.3 AVCC+0.3
SYNC to AGND -0.3 7
VSET to AGND -0.3 7
CS to AGND (DC) -0.3 AVCC+0.3
CS to AGND (40ns transient) -1.0 AVCC+0.3
CS to AGND (20ns transient) -2.0 AVCC+0.3
PGND to AGND -0.3 0.3
Output LO to AGND (DC) -0.3 PVCC+0.3 V
LO to AGND (40ns transient) -1.0 PVCC+0.3
LO to AGND (20ns transient) -2.0 PVCC+0.3
STATUS to AGND(3) -0.3 65
COMP to AGND(2) -0.3 AVCC+0.3
AVCC to AGND -0.3 7
PVCC to AVCC -0.3 0.3
TJ JunctionTemperature(4) -40 150
Tstg Storage Temperature -55 150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The pin voltage is clamped by an internal circuit, and is not specified to have an external voltage applied.
STATUS can go below ground during the STATUS low-to-high transition. The negative voltage on STATUS during this transition is clamped by an internal diode and it does not damage the device.
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

ESD Ratings

MIN MAX UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) –2000 2000 V
Charged device model (CDM), per AEC Q100-011 Corner pins –750 750
Other pins –500 500
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise specified)(1)
MIN NOM MAX UNIT
VVIN Boost input voltage sense 1.5 42 V
VVOUT Boost output voltage sense(2) 5 42 V
VEN EN input 0 42 V
VPVCC PVCC Voltage(3) 4.5 5 5.5 V
VSYNC SYNC Input 0 5.5 V
VCS Current sense Input 0 0.3 V
FSW Typical switching srequency 220 2300 kHz
FSYNC Synchronization pulse frequency 220 2300 kHz
TJ Operating junction temperature(4) –40 150 °C
Operating Ratings are conditions under the device is intended to be functional. For specifications and test conditions, see Electrical Characteristics.
The device requires minimum 5V at VOUT pin to start up
VPVCC should be less than VVOUT + 0.3 V
High junction temperatures degrade operating lifetimes. Operating lifetime is derated for junction temperatures greater than 125°C.

Thermal Information

THERMAL METRIC(1) LM5150-Q1 UNIT
RUM (WQFN)
16 PINS
RθJA Junction-to-ambient thermal resistance 44.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 33.4 °C/W
RθJB Junction-to-board thermal resistance 19.5 °C/W
ΨJT Junction-to-top characterization parameter 0.5 °C/W
ΨJB Junction-to-board characterization parameter 19.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = -40°C to 125°C. Unless otherwise stated, VVOUT = 6.8 V, RT = 9.09 kΩ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ISHUTDOWN(VOUT) VOUT shutdown current VVOUT = 12 V, VEN = 0 V 5 12 µA
ISTANDBY(VOUT) VOUT standby current (PVCC in regulation, STATUS is low) VVOUT = 12 V, VEN = 3.3 V, RSET = 90.9 kΩ 15 25 µA
IWAKEUP(VOUT) VOUT operating current (exclude current into RT resistor) VVOUT = 10.5 V, VEN = 2.5 V, non-switching, RT = 9.09 kΩ 1.2 2.0 mA
ISHUTDOWN(VIN) VIN shutdown current VVIN = 12 V, VEN = 0 V 0.1 0.5 µA
ISTANDBY(VIN) VIN standby current VVIN = 12 V, VEN = 3.3 V, RSET = 29.4 kΩ 0.1 0.5 µA
IWAKEUP(VIN) VIN operating current VVIN = 10.5 V, VEN = 2.5 V, non-switching, RT = 9.09 kΩ 30 45 µA
VCC REGULATOR
VVCC-REG-NOLOAD PVCC regulation VVOUT = 6.0 V, No load, wake-up mode 4.75 5 5.25 V
VVCC-REG-FULLLOAD PVCC regulation VVOUT = 5.0 V, IPVCC = 70 mA 4.5 4.8 V
VVCC-UVLO-RISING AVCC UVLO threshold AVCC rising 4.1 4.3 4.5 V
VVCC-UVLO-FALLING AVCC UVLO threshold AVCC falling 3.9 4.1 4.3 V
VVCC-UVLO-HYS AVCC UVLO hysteresis 0.2 V
IVCC-CL PVCC sourcing current limit VPVCC = 0 V, wake-up mode 75 mA
ENABLE
VEN-RISING Enable threshold EN rising 1.7 2 V
VEN-FALLING Enable threshold EN falling 1 1.3 V
IEN EN bias current VEN = 42 V 100 nA
6.8-V SETTING
VVOUT-REG VOUT regulation target RSET = 29.4 kΩ or 90.9 kΩ 6.66 6.80 6.98 V
VVOUT-WAKEUP VOUT wake-up threshold
(VVOUT-REG+3%)
RSET = 29.4 kΩ or 90.9 kΩ, VOUT falling 6.83 7.00 7.14 V
VVOUT-STANDBY1 VOUT standby threshold
(VVOUT-REG+6%, EC config)
RSET = 90.9 kΩ, VOUT rising 7.02 7.21 7.35 V
VVOUT-STATUS-OFF VOUT status off threshold
(VVOUT-REG +12%, EC config)
RSET = 90.9 kΩ, VOUT rising 7.42 7.62 7.81 V
VVOUT-STANDBY2 VOUT standby threshold
(VVOUT-REG+24%, SS config)
RSET = 29.4 kΩ, VOUT rising 8.22 8.43 8.60 V
VVIN-STANDBY VIN standby threshold
(VVOUT-WAKEUP + 1.0 V, SS config)
RSET = 29.4 kΩ, VIN rising 7.82 8.00 8.19 V
7.5-V SETTING
VVOUT-REG VOUT regulation target RSET = 19.1 kΩ or 71.5 kΩ 7.37 7.50 7.67 V
VVOUT-WAKEUP VOUT wake-up threshold
(VVOUT-REG+3%)
RSET = 19.1 kΩ or 71.5 kΩ, VOUT falling 7.52 7.73 7.88 V
VVOUT-STANDBY1 VOUT standby threshold
(VVOUT-REG+6%, EC config)
RSET = 71.5 kΩ, VOUT rising 7.74 7.95 8.11 V
VVOUT-STATUS-OFF VOUT status off threshold
(VVOUT-REG +12%, EC config)
RSET = 71.5 kΩ, VOUT rising 8.19 8.40 8.61 V
VVOUT-STANDBY2 VOUT standby threshold
(VVOUT-REG+24%, SS config)
RSET = 19.1 kΩ, VOUT rising 9.07 9.30 9.46 V
VVIN-STANDBY VIN standby threshold
(VVOUT-WAKEUP + 1.0 V, SS config)
RSET = 19.1 kΩ, VIN rising 8.50 8.73 8.93 V
8.5-V SETTING
VVOUT-REG VOUT regulation target RSET = 9.53 kΩ or 54.9 kΩ 8.37 8.50 8.69 V
VVOUT-WAKEUP VOUT wake-up threshold
(VVOUT-REG+3%)
RSET = 9.53 kΩ or 54.9 kΩ, VOUT falling 8.52 8.76 8.93 V
VVOUT-STANDBY1 VOUT standby threshold
(VVOUT-REG+6%, EC config)
RSET = 54.9 kΩ, VOUT rising 8.78 9.01 9.19 V
VVOUT-STATUS-OFF VOUT status off threshold
(VVOUT-REG +12%, EC config)
RSET = 54.9 kΩ, VOUT rising 9.28 9.52 9.75 V
VVOUT-STANDBY2 VOUT standby threshold
(VVOUT-REG+24%, SS config)
RSET = 9.53 kΩ, VOUT rising 10.29 10.54 10.72 V
VVIN-STANDBY VIN standby threshold
(VVOUT-WAKEUP + 1.0 V, SS config)
RSET = 9.53 kΩ, VIN rising 9.50 9.76 9.98 V
10.5-V SETTING
VVOUT-REG VOUT regulation target RSET = GND or 41.2 kΩ 10.31 10.50 10.75 V
VVOUT-WAKEUP VOUT wake-up threshold
(VVOUT-REG+3%)
RSET = GND or 41.2 kΩ, VOUT falling 10.53 10.82 11.02 V
VVOUT-STANDBY1 VOUT standby threshold
(VVOUT-REG+6%, EC config)
RSET = 41.2 kΩ, VOUT rising 10.84 11.13 11.33 V
VVOUT-STATUS-OFF VOUT status off threshold
(VVOUT-REG +12%, EC config)
RSET = 41.2 kΩ, VOUT rising 11.46 11.76 12.04 V
VVOUT-STANDBY2 VOUT standby threshold
(VVOUT-REG+24%, SS config)
RSET = GND, VOUT rising 12.70 13.02 13.24 V
VVIN-STANDBY VIN standby threshold
(VVOUT-WAKEUP + 1.0 V, SS config)
RSET = GND, VIN rising 11.47 11.82 12.11 V
RT
VRT-REG RT regulation voltage 1.2 V
CLOCK SYNCHRONIZATION
VSYNC-RISING SYNC rising threshold 2.0 2.4 V
VSYNC-FALLING SYNC falling threshold 0.4 1.5 V
PULSE WIDTH MODULATION AND OSCILLATOR
FSW1 Switching frequency RT = 93.1 kΩ 204 239 270 kHz
FSW2 Switching frequency RT = 9.09 kΩ 2100 2300 2500 kHz
FSW3 Switching frequency RT = 9.09 kΩ,
FSYNC = 2.0 MHz
2000 kHz
TON-MIN Forced minimum on-time SS config, VCOMP = 0 V 30 50 70 ns
DMIN Minimum duty cycle limit (EC config) RT = 9.09 kΩ, VVIN = 1.5 V, VVOUT = 6.8 V, VCOMP = 0 V 60 %
RT = 93.1 kΩ, VVIN = 8.4 V, VVOUT = 10.5 V, VCOMP = 0 V 16 %
DMAX Maximum duty cycle limit SS config, RT = 9.09 kΩ 83 87 91.5 %
EC config, RT = 93.1 kΩ 83 87 91.5 %
CURRENT SENSE
VCSTH Current limit threshold (CS-AGND)(1) VVIN = 5.1 V, VVOUT = 6.8 V at 25% DC 102 120 138 mV
VVIN = 3.4 V, VVOUT = 6.8 V at 50% DC 102 120 138 mV
VVIN = 1.7 V, VVOUT = 6.8 V at 75% DC 102 120 138 mV
ERROR AMPLIFIER
Gm Transconductance 2 mA/V
COMP souring current VCOMP = 0 V 312 µA
COMP sinking current VCOMP = 1.5 V 120 µA
COMP clamp voltage 2.4 2.6 V
COMP to PWM offset 0.3 V
STATUS
Low-state voltage drop 1-mA sinking 0.1 V
STATUS rise to LO delay 5-kΩ pullup to 5 V 4 5 6 µs
MOSFET DRIVER
High-state voltage drop 50-mA sinking 0.075 V
Low-state voltage drop 50-mA sourcing 0.055 V
THERMAL SHUTDOWN (TSD)
Thermal shutdown threshold Temperature rising 175 °C
Thermal shutdown hysteresis 15 °C
VCL at the current limit comparator input is 10 x VCSTH

Typical Characteristics

LM5150-Q1 D001_SNVSAP6.gif Figure 1. Peak Inductor Current vs Supply Voltage
(FSW = 250 kHz, RS = 8 mΩ)
LM5150-Q1 D003_SNVSAP6.gif Figure 3. VPVCC vs IPVCC (VOUT = 6 V)
LM5150-Q1 D005_SNVSAP6.gif Figure 5. Frequency vs RT
LM5150-Q1 D007_SNVSAP6.gif Figure 7. IVOUT vs Temperature
LM5150-Q1 D002_SNVSAP6.gif Figure 2. Current Limit Threshold at CS vs Duty Cycle
LM5150-Q1 D004_SNVSAP6.gif Figure 4. VPVCC vs VVOUT (EN = 3.3 V, IPVCC = 10 mA, VOUT Rising)
LM5150-Q1 D006_SNVSAP6.gif Figure 6. Duty Cycle Limit in EC Configuration vs VVIN
LM5150-Q1 D008_SNVSAP6.gif Figure 8. Efficiency vs Load Current
(VLOAD = 6.8 V, FSW = 440 kHz, SS Configuration)