Table 3. Design Parameters

8.2.1.2.1 Custom Design With WEBENCH® Tools

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8.2.1.2.2 Output Resistor Divider Selection

With the required output voltage set point at 12 V and V_FB = 2 V (typical), the ratio of R8 (R_FB1) to R7 (R_FB2) can be calculated using Equation 6:

Equation 6.

The resistor ratio calculates to be 5:1. Standard values of R8 (R_FB1) = 2 kΩ and R7 (R_FB2 ) =10 kΩ are chosen. Higher or lower resistor values could be used as long as the ratio of 5:1 is maintained.

8.2.1.2.3 Frequency Selection

The duty cycle required to maintain output regulation at the minimum input voltage restricts the maximum switching frequency of LM5161. The maximum value of the minimum forced OFF-time T_OFF,min (max), limits the duty cycle and therefore the switching frequency. The maximum frequency that avoids output dropout at minimum input voltage can be calculated from Equation 7.

Equation 7.

For this design example, the maximum frequency based on the minimum OFF-time limitation for T_OFF,min(typ) = 170 ns is calculated to be F_{SW,max(@VIN,min)} = 1.2 MHz. This value is above 1 MHz, the maximum possible operating frequency of the LM5161. Therefore, the minimum OFF-time parameter restricts the maximum achievable switching frequency calculation in this application.

At the maximum input voltage, the maximum switching frequency of LM5161 is restricted by the minimum ON-time, T_ON,min which limits the minimum duty cycle of the converter. The maximum frequency at maximum input voltage can be calculated using Equation 8.

Equation 8.

Using Equation 8 and T_ON,min (typ) = 150 ns, the maximum achievable switching frequency is F_{SW,max(@VIN,min)}= 1000 kHz. Taking this value as the maximum possible operational switching frequency over the input voltage range in this application, a nominal switching frequency of F_SW = 300 kHz is chosen for this design.

The value of the resistor, R_ON sets the nominal switching frequency based on Equation 9.

Equation 9.

For this particular application with F_SW = 300 kHz, R_ON calculates to be 396 kΩ . Selecting a standard value for R1 (R_ON) = 402 kΩ (±1%) results in a nominal frequency of 296 kHz. The resistor value may need to adjusted further in order to achieve the required switching frequency as the switching frequency in Constant ON-Time converters varies slightly(±10%) with input voltage and/or output current. Operation at a lower nominal switching frequency will result in higher efficiency but increase in the inductor and capacitor values leading to a larger total solution size.

8.2.1.2.4 Inductor Selection

The inductor is selected to limit the inductor ripple current to a value between 20 and 40 percent of the maximum load current. The minimum value of the inductor required in this application can be calculated from Equation 10:

Equation 10.

Based on Equation 10 , the minimum value of the inductor is calculated to be 85 µH for V_IN = 80-V (max) and inductor current ripple will be 40 percent of the maximum load current. Allowing some margin for inductance variation and inductor saturation, a higher standard value of L1 (L) = 100 µH is selected for this design.

The peak inductor current at maximum load must be smaller than the minimum current limit threshold of the high side FET as given in Electrical Characteristics table. The inductor current ripple at any input voltage is given by:

Equation 11.

The peak-to-peak inductor current ripple is calculated to be 81 mA and 341 mA at the minimum and maximum input voltages respectively. The maximum peak inductor current in the buck FET is given by Equation 12:

Equation 12.

In this design with maximum output current of 1-A, the maximum peak inductor current is calculated to be approximately 1.17 A at V_IN,max = 80 V, which is less than the minimum high-side FET current limit threshold.

The saturation current of the inductor must also be carefully considered. The peak value of the inductor current will be bound by the high side FET current limit during overload or short circuit conditions. Based on the high side FET current limit specification in the Electrical Characteristics, an inductor with saturation current rating above 1.9 A (max) should be selected.

8.2.1.2.5 Output Capacitor Selection

The output capacitor is selected to limit the capacitive ripple at the output of the regulator. Maximum capacitive ripple is observed at maximum input voltage. The output capacitance required for a ripple voltage ∆V_O across the capacitor is given by Equation 13.

Equation 13.

Substituting ∆V_{O, ripple} = 10 mV gives C_OUT = 15 μF. Two standard 10 μF ceramic capacitors in parallel (C11, C12) are selected. An X7R type capacitor with a voltage rating 25 V or higher should be used for C_OUT (C11, C12) to limit the reduction of capacitance due to dc bias voltage.

8.2.1.2.6 Series Ripple Resistor - R_ESR (FPWM = 1)

If the FPWM = 1, i.e. the FPWM pin is pulled high as when connected to V_CC, a series resistor in series with the output capacitor or the external ripple injection circuit must be selected such that sufficient ripple injection (> 25mV) is ensured at the feedback pin FB. The ripple produced by R_ESR is proportional to the inductor current ripple, and therefore, R_ESR should be chosen for minimum inductor current ripple which occurs at minimum input voltage. The R_ESR is calculated by Equation 14.

Equation 14.

With V_O = 12 V, V_REF = 2 V and ΔI_{L, min} = 81 mA (at V_{IN, min}= 15 V) as calculated in Equation 11, Equation 14 requires an R_ESR greater than or equal to 1.87 Ω. Selecting R4 (R_ESR) = 2 Ω results in approximately 700 mV of maximum output voltage ripple at V_IN,max. However due to the internal DC Error correction loop, the load and line regulation will be much improved, despite the addition of a large R_ESR in the circuit. For applications which require even lower output voltage ripple, Type 2 or Type 3 ripple injection circuits must be used, as described in Ripple Configuration. In this design example, with the FPWM =1 (i.e. the FPWM pin is pulled up to V_CC) a 0 Ω ESR resistor is selected and the external Type 3 ripple injection circuit is used.

8.2.1.2.7 VCC and Bootstrap Capacitor

The VCC capacitor charges the bootstrap capacitor during the OFF-time of the high-side switch and powers internal logic circuits and the low side sync FET gate driver. The bootstrap capacitor biases the high-side gate driver during the high-side FET ON-time. A good value for C13 (C_VCC) is 1 µF. A good choice for C1 (C_BST) is 10 nF. Both must be high quality X7R ceramic capacitors.

8.2.1.2.8 Input Capacitor Selection

The input capacitor must be large enough to limit the input voltage ripple to an acceptable level. Equation 15 provides the input capacitance C_IN required for a worst case input ripple of ∆V_{IN, ripple}.

Equation 15.

C_IN (C4, C6) supplies most of the switch current during the ON-time to limit the voltage ripple at the VIN pin. At maximum load current, when the buck switch turns on, the current into the VIN pin quickly increases to the valley current of the inductor ripple and then ramps up to the peak of the inductor ripple during the ON-time of the high-side FET. The average current during the ON-time is the output load current. For a worst-case calculation, C_IN must supply this average load current during the maximum ON-time, without letting the voltage at VIN drop more than the desired input ripple. For this design, the input voltage drop is limited to 0.5 V and the value of C_IN is calculated using Equation 15.

Based on Equation 15, the value of the input capacitor is calculated to be approximately 1.68 µF at D = 0.5. Taking into account the decrease in capacitance over an applied voltage, two standard value ceramic capacitors of 2.2 μF are selected for C4 and C6. The input capacitors should be rated for the maximum input voltage under all operating and transient conditions. A 100-V, X7R dielectric was selected for this design.

A third input capacitor C5 is needed in this design as a bypass path for the high frequency component of the input switching current. The value of C5 is 0.1 μF and this bypass capacitor must be placed directly across VIN and PGND (pin 3 and 2) near the IC. The C_IN values and location are critical to reducing switching noise and transients.

8.2.1.2.9 Soft-Start Capacitor Selection

The capacitor at the SS pin determines the soft-start time, that is the time for the output voltage to reach its final steady state value. The capacitor value is determined from Equation 16:

Equation 16.

With C9 (C_SS) set at 22 nF and the Vss = 2 V, I_SS = 10 µA, the T_Startup should measure approximately 4 ms.

8.2.1.2.10 EN/UVLO Resistor Selection

The UVLO resistors R3 (R_UV2) and R9 (R_UV1) set the input undervoltage lockout threshold and hysteresis according to Equation 17 and Equation 18:

Equation 17.

and,

Equation 18.

From the Electrical Characteristics, I_UVLO(HYS) = 20 μA (typical). To design for V_IN rising threshold (V_{IN, UVLO(rising)}) at 15 V and EN/UVLO hysteresis of 1.5 V, Equation 17 and Equation 18 yield R_UV1 = 6.81 kΩ and R_UV2 = 75 kΩ . Selecting 1% standard value of R9 (R_UV1) = 6.81 kΩ and R3 (R_UV2) = 75 kΩ results in UVLO threshold (rising) and hysteresis of 14.9 V and 1.5 V respectively.

Table 4. Design Parameters

8.2.2.2.1 Selection of V_OUT and Turns Ratio

The primary output voltage in a Fly-Buck converter should be no more than one half of the minimum input voltage. Therefore, at the minimum V_IN of 36 V, the primary output voltage ( V_OUT ) should be no higher than 18 V. The isolated output voltage of V_OUTISO in Figure 34 is set at 12 V by selecting a transformer with a turns ratio (N₁:N₂ :: N_PRI:N_SEC) of 1:1. Using this turns ratio, the required primary output voltage V_OUT is calculated in Equation 19:

Equation 19.

The 0.7 V (V_FD1) added to V_OUTISO in Equation 19 represents the forward voltage drop of the secondary rectifier diode. By setting the primary output voltage V_OUT to 12.7-V by selecting the correct feedback resistors, the secondary voltage is regulated at 12-V nominally. Adjustment of the primary side V_OUT may be required to compensate for voltage errors due to the leakage inductance of the transformer, the resistance of the transformer windings, the diode drop in the power path on the secondary side and the low-side FET of the LM5161.

8.2.2.2.2 Secondary Rectifier Diode

The secondary side rectifier diode must block the maximum input voltage reflected at secondary side switch node. The minimum diode reverse voltage V_(RD1) rating is given in Equation 20:

Equation 20.

A diode of 100-V or higher reverse voltage rating must be selected in this application. If the input voltage (V_IN) has transients above the normal operating maximum input voltage of 72 V, then the worst-case transient input voltage must be used in the Equation 20 while selecting the secondary side rectifier diode.

8.2.2.2.3 External Ripple Circuit

The FPWM pin in the LM5161 should never be grounded or left open when used in a Fly-Buck application. Type 3 ripple circuit is required for Fly-Buck applications. Follow the design procedure used in the buck converter for selecting the Type 3 ripple injection components. See Ripple Configuration for ripple design information.

8.2.2.2.4 Output Capacitor (C_VISO)

The Fly-Buck output capacitor conducts higher ripple current than a buck converter output capacitor. The ripple voltage across the isolated output capacitor is calculated based on the time the rectifier diode is off. During this time the entire output current is supplied by the output capacitor. The required capacitance for the worst-case ripple voltage can be calculated using Equation 21 where, ΔV_ISO is the expected ripple voltage at the secondary output.

Equation 21.

Equation 21 is an approximation and ignores the ripple components associated with ESR and ESL of the output capacitor. For a ΔV_ISO = 100 mV, Equation 21 requires C_VISO = 11.12 µF. When selecting the C_VISO output capacitors (C2 and C3 in the Figure 34), the DC bias must be considered in order to ensure sufficient capacitance over the output voltage.