SNVSAJ3B March 2016 – February 2017 LM5165-Q1
The LM5165-Q1 converter is an easy-to-use synchronous buck DC-DC regulator that operates from a 3-V to
65-V supply voltage. The device is intended for step-down conversions from 3.3-V, 5-V, 12-V, 24-V, and 48-V unregulated, semi-regulated and fully-regulated supply rails. With integrated high-side and low-side power MOSFETs, the LM5165-Q1 delivers up to 150-mA DC load current with high efficiency and ultra-low input quiescent current in a very small solution size. Designed for simple implementation, a choice of operating modes offers flexibility to optimize its usage according to the target application. In constant on-time (COT) mode of operation, ideal for low-noise, high current, fast load transient requirements, the device operates with predictive on-time switching pulse. A quasi-fixed switching frequency over the input voltage range is achieved by using an input voltage feedforward to set the on-time. Alternatively, pulse frequency modulation (PFM) mode, complemented by an adjustable peak current limit, achieves exceptional light-load efficiency performance. Control loop compensation is not required with either operating mode, reducing design time and external component count.
The LM5165-Q1 incorporates other features for comprehensive system requirements, including an open-drain Power Good circuit for power-rail sequencing and fault reporting, internally-fixed or externally-adjustable soft-start, monotonic start-up into prebiased loads, precision enable with customizable hysteresis for programmable line undervoltage lockout (UVLO), adjustable cycle-by-cycle current limit for optimal inductor sizing, and thermal shutdown with automatic recovery. These features enable a flexible and easy-to-use platform for a wide range of applications. The pin arrangement is designed for simple Layout, requiring only a few external components.
The LM5165-Q1 is a step-down buck converter with integrated high-side PMOS buck switch and low-side NMOS synchronous switch. During the high-side MOSFET on-time, the SW voltage VSW swings up to approximately VIN, and the inductor current increases with slope (VIN – VOUT)/LF. When the high-side MOSFET is turned off by the control logic, the low-side MOSFET turns on after an adaptive deadtime. Inductor current flows through the low-side MOSFET with slope –VOUT/LF. Duty cycle D is defined as TON/TSW, where TON is the high-side MOSFET conduction time and TSW is the switching period.
The LM5165-Q1 operates in PFM mode when RT is shorted to GND. Configured as such, the LM5165-Q1 behaves as a hysteretic voltage regulator operating in boundary conduction mode, controlling the output voltage within upper and lower hysteresis levels according to the PFM feedback comparator hysteresis of 10 mV. Figure 33 is a representation of the relevant output voltage and inductor current waveforms. The LM5165-Q1 provides the required switching pulses to recharge the output capacitor, followed by a sleep period where most of the internal circuits are shut off. The load current is supported by the output capacitor during this time, and the LM5165-Q1 current consumption approaches the sleep quiescent current of 10.5 µA. The sleep period duration depends on load current and output capacitance.
When operating in PFM mode at given input and output voltages, the chosen filter inductance dictates the PFM pulse frequency in Equation 1:
Configured in COT mode, the LM5165-Q1 based converter turns on the high-side MOSFET with on-time inversely proportional to VIN to operate with essentially fixed switching frequency when in continuous conduction mode (CCM). Diode emulation mode (DEM) prevents negative inductor current, and pulse skipping maintains highest efficiency at light load currents by decreasing the effective switching frequency. The COT-controlled LM5165-Q1 waveforms in CCM and DEM are represented in Figure 34. The PWM on-time is set by resistor RRT connected from RT to GND as shown in Figure 32. The control loop maintains a constant output voltage by adjusting the PWM off-time.
|FSW (kHz)||RRT (kΩ)|
|VOUT = 1.8 V||VOUT = 3.3 V||VOUT = 5 V||VOUT = 12 V|
The choice of control mode and switching frequency requires a compromise between conversion efficiency, quiescent current, and passive component size. Lower switching frequency implies reduced switching losses (including gate charge losses, transition losses, and so forth) and higher overall efficiency. Higher switching frequency, on the other hand, implies a smaller LC output filter and hence a more compact design. Lower inductance also helps transient response as the large-signal slew rate of inductor current increases. The ideal switching frequency in a given application is a tradeoff and thus is determined on a case-by-case basis. It relates to the input voltage, output voltage, most frequent load current level(s), external component choices, and circuit size requirement. At light loads, the PFM converter has a relatively longer sleep time interval and thus operates with lower input quiescent current and higher efficiency.
Diode emulation mode (DEM) operation occurs when the low-side MOSFET switches off as inductor valley current reaches zero. Here, the load current is less than half of the peak-to-peak inductor current ripple in CCM. Turning off the low-side MOSFET at zero current reduces switching loss, and preventing negative current conduction reduces conduction loss. Power conversion efficiency is thus higher in a DEM converter than an equivalent forced-PWM CCM converter. With DEM operation, the duration that both power MOSFETs remain off progressively increases as load current decreases.
If RDSON1 and RDSON2 are the high-side and low-side MOSFET on-state resistances, respectively, and RDCR is the inductor DC resistance, the duty cycle in COT (CCM) or PFM mode is given by Equation 3.
The LM5165-Q1 offers a low input voltage to output voltage dropout by engaging the high-side MOSFET at 100% duty cycle. In COT mode, a frequency foldback feature effectively extends maximum duty cycle to 100% during low dropout conditions or load-on transients. Based on the 4-mV FB comparator dropout hysteresis, the duty cycle extends as needed at low input voltage conditions, corresponding to lower switching frequency. The PWM on-time extends based on the requirement that the FB voltage exceeds the dropout hysteresis during a given on-time. 100% duty cycle operation is eventually reached as the input voltage decreases towards the output setpoint. The output voltage stays in regulation at a lower supply voltage, thus achieving an extremely low dropout voltage.
Note that PFM mode operation provides an inherently natural transition to 100% duty cycle if needed for low dropout applications.
Use Equation 4 to calculate the minimum input voltage to maintain output regulation.
Three voltage feedback options are available: the fixed 3.3-V and 5-V versions include internal feedback resistors that sense the output directly through the VOUT pin; the adjustable voltage option senses the output through an external resistor divider connected from the output to the FB pin.
The LM5165-Q1 voltage regulation loop regulates the output voltage by maintaining the FB voltage equal to the internal reference voltage, VREF1. A resistor divider programs the ratio from output voltage VOUT to FB. For a target VOUT setpoint, calculate RFB2 based on the selected RFB1 using Equation 5.
Selecting RFB1 of 100 kΩ is recommended for most applications. A larger RFB1 consumes less DC current, mandatory if light-load efficiency is critical. High feedback resistances generally require more careful feedback path PCB layout. It is important to route the feedback trace away from the noisy area of the PCB. For more layout recommendations, see Layout.
The LM5165-Q1 manages overcurrent conditions by cycle-by-cycle current limiting of the peak inductor current. The current sensed in the high-side MOSFET is compared every switching cycle to the current limit threshold set by the ILIM pin. Current is sensed after a leading-edge blanking time following the high-side MOSFET turnon transition. The propagation delay of current limit comparator is 100 ns.
Four programmable peak current levels are available: 60 mA, 120 mA, 180 mA and 240 mA, corresponding to resistors of 100 kΩ, 56.2 kΩ, 24.9 kΩ and 0 Ω connected at the ILIM pin, respectively. In turn, 25-mA, 50-mA, 75-mA, and 100-mA output current levels in boundary conduction mode PFM operation are possible, respectively.
Note that in PFM mode, the inductor current ramps from zero to the chosen peak threshold every switching cycle. Consequently, the maximum output current is equal to half the peak inductor current. Meanwhile, the corresponding output current capability in COT mode is higher as the ripple current is determined by the input and output voltage and the chosen inductance.
The precision EN input supports adjustable input undervoltage lockout (UVLO) with hysteresis programmed independently through the HYS pin for application specific power-up and power-down requirements. EN connects to a comparator-based input referenced to a 1.212-V bandgap voltage with 68-mV hysteresis. An external logic signal can be used to drive the EN input to toggle the output on and off and for system sequencing or protection. The simplest way to enable the LM5165's operation is to connect EN directly to VIN. This allows the LM5165-Q1 to start up when VIN is within its valid operating range. However, many applications benefit from using a resistor divider RUV1 and RUV2 as shown in Figure 35 to establish a precision UVLO level. In tandem with the EN setting, use HYS to increase the voltage hysteresis as needed.
There is also a low IQ shutdown mode when EN is pulled below a base-emitter voltage drop (approximately 0.6 V at room temperature). If EN is below this hard shutdown threshold, the internal LDO regulator powers off and the internal bias supply rail collapses, shutting down the bias currents of the LM5165-Q1. The LM5165-Q1 operates in standby mode when the EN voltage is between the hard shutdown and precision enable thresholds.
The LM5165-Q1 provides a PGOOD flag pin to indicate when the output voltage is within the regulation level. Use the PGOOD signal for start-up sequencing of downstream converters, as shown in Figure 36, or for fault protection and output monitoring. PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater than 12 V. Typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to decrease the voltage from a higher voltage pullup rail.
When the FB voltage exceeds 94% of the internal reference VREF1, the internal PGOOD switch turns off and PGOOD can be pulled high by the external pullup. If the FB voltage falls below 87% of VREF1, the internal PGOOD switch turns on, and PGOOD is pulled low to indicate that the output voltage is out of regulation. The rising edge of PGOOD has a built-in deglitch delay of 5 µs.
The LM5165-Q1 has a flexible and easy-to-use soft-start control pin, SS. The soft-start feature prevents inrush current impacting the LM5165-Q1 and the input supply when power is first applied. Soft start is achieved by slowly ramping up the target regulation voltage when the device is first enabled or powered up. Selectable and adjustable start-up timing options include minimum delay (no soft-start), 900-µs internally fixed soft start, and an externally programmable soft start.
The simplest way to use the LM5165-Q1 is to leave the SS pin open. The LM5165-Q1 employs the internal soft-start control ramp and starts up to the regulated output voltage in 900 µs. In applications with a large amount of output capacitance, higher VOUT, or other special requirements, extend the soft-start time by connecting an external capacitor CSS from SS to GND. Longer soft-start time further reduces the supply current needed to charge the output capacitors and supply any output loading. An internal current source ISS of 10 µA charges CSS and generates a ramp to control the ramp rate of the output voltage. Use Equation 8 to calculate the CSS capacitance for a desired soft-start time tSS.
CSS is discharged by an internal FET when VOUT is shutdown by EN, UVLO, or thermal shutdown.
It is desirable in some applications for the output voltage to reach its nominal setpoint in the shortest possible time. Connecting a 100-kΩ resistor from SS to GND disables the soft-start circuit, and the LM5165-Q1 operates in current limit during start-up to rapidly charge the output capacitance.
As negative inductor current is prevented, the LM5165-Q1 is capable of start-up into prebiased output conditions. With a prebiased output voltage, the LM5165-Q1 waits until the soft-start ramp allows regulation above the prebiased voltage and then follows the soft-start ramp to the regulation setpoint.
Thermal shutdown is an integrated self-protection to limit junction temperature and prevent damage related to overheating. Thermal shutdown turns off the device when the junction temperature exceeds 170°C to prevent further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the LM5165-Q1 restarts when the junction temperature falls to 160°C.
The EN pin provides ON and OFF control for the LM5165-Q1. When VEN is below approximately 0.6 V, the device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in shutdown mode drops to 4.6 µA at VIN = 12 V. The LM5165-Q1 also employs internal bias rail undervoltage protection. If the internal bias supply voltage is below its UV threshold, the regulator remains off.
The internal bias rail LDO has a lower enable threshold than the regulator itself. When VEN is above 0.6 V and below the precision enable threshold (1.212 V typically), the internal LDO is on and regulating. The precision enable circuitry is turned on once the internal VCC is above its UV threshold. The switching action and voltage regulation are not enabled until VEN rises above the precision enable threshold.
The LM5165-Q1 is in active mode when VEN is above the precision enable threshold and the internal bias rail is above its UV threshold. In COT active mode, the LM5165-Q1 is in one of three modes depending on the load current:
Similarly, the LM5165-Q1 is in PFM active mode when VEN and the internal bias rail are above the relevant thresholds, FB has fallen below the lower hysteresis level (VREF1), and boundary conduction mode is recharging the output capacitor to the upper hysteresis level (VREF2). There is a 4-µs wake-up delay from sleep to active states.
The LM5165-Q1 is in PFM sleep mode when VEN and the internal bias rail are above the relevant threshold levels, VFB has exceeded the upper hysteresis level (VREF2), and the output capacitor is sourcing the load current. In PFM sleep mode, the LM5165-Q1 operates with very low quiescent current.