The over-temperature protection circuit measures the temperature of the driver die and trips if the temperature exceeds the over-temperature threshold (typically 165 °C). Upon an over-temperature condition, the GaN device is held off and a fault is latched. To resume operation, the temperature must fall below the lower thermal shut down threshold and the input must be held low for typical 350 µs to reset the latched fault.
The FAULT output is a push-pull output indicating the readiness and fault status of the driver. It is held low when starting up until the safety FET is turned on. In an OCP or OTP fault condition, it is held low until the fault latches are reset or fault is cleared. If the power supplies go below the UVLO thresholds, power transistor switching is disabled and FAULT is held low until the power supplies recover. Specifically, during VDD UVLO happens, Buck-boost converter, LDO 5V and GaN FET will be disabled; similarly, LDO 5V UVLO will trigger Buck-boost converter to stop operation and disable the FET; and VNEG UVLO will cause the FET to be disabled.