SNLS270L August   2007  – January 2016 LMH0356


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 AC Electrical Characteristics
    7. 7.7 AC Timing Requirements
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Functional Block Description
        1. Serial Data Input and Outputs
        2. Operating Serial Data Rates
        3. Serial Data Clock/Serial Data 2 Output
      2. 8.3.2 Control Inputs and Indicator Outputs
        1. Serial Data Rate Selector
        2. Serial Data Input Selector
        3. Lock Detect
        4. OUTPUT MUTE
        5. Bypass/AUTO BYPASS
        6. SD/HD
        7. SCO_EN
        8. ENABLE
        9. Crystal or External Clock Reference
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Input Output Interfacing
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Supports SMPTE ST-424, ST-292, and ST-259 Serial Digital Video Standards
  • Supports 270-Mbps, 1.483-Gbps, 1.485-Gbps, 2.967-Gbps, and 2.97-Gbps Serial Data Rate Operation
  • Supports DVB-ASI at 270 Mbps
  • Single 3.3-V Supply Operation
  • 430-mW Typical Power Consumption
  • Integrated 4:1 Multiplexed Input
  • 0 to 30-inch FR4 Equalizer on Each Multiplexed Input
  • Two Differential, Reclocked Outputs
  • Choice of Second Reclocked Output or Recovered Clock Output
  • Single 27-MHz External Crystal or Reference Clock Input
  • Manual Rate Select Input
  • SD/HD Operating Rate Indicator Output
  • Lock Detect Indicator Output
  • Output Mute Function for Data and Clock
  • Auto/Manual Reclocker Bypass
  • Power Saver Mode With Device Power-Down Control (10-mW Typical Power Consumption in Disabled State)
  • Differential LVPECL-Compatible Serial Data Inputs and Outputs
  • LVCMOS Control Inputs and Indicator Outputs
  • 48-Pin WQFN or 40-Pin WQFN Package
  • Industrial Temperature Range: –40°C to 85°C
  • 48-Pin WQFN Version Footprint-Compatible with the LMH0056 and LMH0036

2 Applications

  • SDTV/HDTV and 3-Gbps Serial Digital Video Interfaces for:
    • Digital Video Routers and Switchers
    • Digital Video Processing and Editing Equipment
    • DVB-ASI Equipment
    • Video Standards and Format Converters

3 Description

The LMH0356 3-Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs retimes serial digital video data conforming to the SMPTE ST-424, ST-292, and ST-259 standards. The LMH0356 operates at serial data rates of 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps. The LMH0356 supports DVB-ASI operation at 270 Mbps. The LMH0356 includes an integrated 4:1 input multiplexer for selecting one of four input data streams for retiming. In addition, the four inputs of the LMH0356 each have an FR4 equalizer capable of equalizing 0 to 30 inches of FR4 trace length.

The LMH0356 automatically detects the incoming data rate and adjusts itself to retime the incoming data to suppress accumulated jitter. The LMH0356 recovers the serial data-rate clock and optionally provides it as an output. The LMH0356 has two differential serial data outputs; the second output may be selected as a low-jitter, data-rate clock output. Controls and indicators are: serial clock or second serial data output select, manual rate select input, SD/HD rate indicator output, lock detect output, auto/manual data bypass, output mute, and device enable. The serial data inputs, outputs, and serial clock outputs are differential LVPECL compatible. The CML serial data and serial clock outputs are suitable for driving 100-Ω differentially terminated networks. The control logic inputs and outputs are LVCMOS compatible.

Device Information(1)

LMH0356 WQFN (40) 5.00 mm x 5.00 mm
WQFN (48) 7.00 mm x 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Functional Block Diagram

LMH0356 30016703.gif

4 Revision History

Changes from K Revision (April 2013) to L Revision

  • Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go