SNLS474E February   2015  – June 2018 LMH1218

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified SPI Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD
    2.     Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface AC Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Loss of Signal Detector
      2. 7.3.2 Continuous Time Linear Equalizer (CTLE)
      3. 7.3.3 2:1 Multiplexer
      4. 7.3.4 Clock and Data Recovery
      5. 7.3.5 Eye Opening Monitor (EOM)
      6. 7.3.6 Fast EOM
        1. 7.3.6.1 SMBus Fast EOM Operation
        2. 7.3.6.2 SPI Fast EOM Operation
      7. 7.3.7 LMH1218 Device Configuration
        1. 7.3.7.1 MODE_SEL
        2. 7.3.7.2 ENABLE
        3. 7.3.7.3 LOS_INT_N
        4. 7.3.7.4 LOCK
        5. 7.3.7.5 SMBus MODE
        6. 7.3.7.6 SMBus READ/WRITE Transaction
        7. 7.3.7.7 SPI Mode
          1. 7.3.7.7.1 SPI READ/WRITE Transaction
          2. 7.3.7.7.2 SPI Write Transaction Format
          3. 7.3.7.7.3 SPI Read Transaction Format
        8. 7.3.7.8 SPI Daisy Chain
          1. 7.3.7.8.1 SPI Daisy Chain Write Example
          2. 7.3.7.8.2 SPI Daisy Chain Write Read Example
            1. 7.3.7.8.2.1 SPI Daisy Chain Length of Daisy Chain Illustration
      8. 7.3.8 Power-On Reset
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 Global Registers
      2. 7.6.2 Receiver Registers
      3. 7.6.3 CDR Registers
      4. 7.6.4 Transmitter Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Guidance for All Applications
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
    4. 8.4 Initialization Set Up
      1. 8.4.1 Selective Data Rate Lock
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Solder Profile
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.3 CDR Registers

Table 7. CDR Registers

REGISTER
NAME		 BITS FIELD REGISTER
ADDRESS		 DEFAULT R/RW DESCRIPTION
Output_Mux_OV Reg 0x09 Channel 0x00 Output Data Mux Override
7 Reserved 0 RW
6 Reserved 0 RW
5 Reg_bypass_pfd_ovd 0 RW 1: Enable values from 0x1E[7:5] & 0x1C[7:5] to control output mux
0: Register 0x1C[3:2] determines the output selection
4 Reserved 0 RW
3 Reserved 0 RW
2 Reserved 0 RW
1 Reserved 0 RW
0 Reserved 0 RW
CDR_Reset Reg 0x0A Channel 0x50 CDR State Machine Reset
7 Reserved 0 RW
6 Reserved 1 RW
5 Reserved 0 RW
4 Reserved 1 RW
3 reg_cdr_reset_ov 0 RW 1: Enable 0x0A[2] to control CDR Reset
0: Disable CDR Reset
2 reg_cdr_reset_sm 0 RW 1: Enable CDR Reset if 0x0A[3] = 1'b
0: Disable CDR Reset if 0x0A[3] = 1'b
1 Reserved 0 RW
0 Reserved 0 RW
CDR_Status Reg 0x0C Channel 0x08 CDR Status Control
7 reg_sh_status_control[3] 0 RW Determines what is shown in Reg 0x02. Note LMH1218 Programming Guide (SNLU174) for details
6 reg_sh_status_control[2] 0 RW
5 reg_sh_status_control[1] 0 RW
4 reg_sh_status_control[0] 0 RW
3 Reserved 1 RW
2 Reserved 0 RW
1 Reserved 0 RW
0 Reserved 0 RW
EOM_Vrange Reg 0x11 Channel 0xE0 EOM Vrange Setting and EOM Power Down Control
7 eom_sel_vrange[1] 11 RW Sets eye monitor ADC granularity if 0x2C[6] =0'b
00: 3.125 mV
01: 6.25 mV
10: 9.375 mV
11: 12.5 mV
6 eom_sel_vrange[0]
5 eom_PD 1 RW 0: EOM Operational
1: Power down EOM
4 Reserved 0 RW
3 Reserved 0 RW
2 Reserved 0 RW
1 Reserved 0 RW
0 Reserved 0 RW
Full Temperature Range Reg 0x16 Channel 0x7A Temperature Range Setting
7 Reserved 0 RW At power-up, this register needs to be set to 0x25. See initialization set up
6 Reserved 1 RW
5 Reserved 1 RW
4 Reserved 1 RW
3 Reserved 1 RW
2 Reserved 0 RW
1 Reserved 1 RW
0 Reserved 0 RW
HEO_VEO_OV Reg 0x23 Channel 0x40
7 eom_get_heo_veo_ov 0 RW 1: Enable reg 0x24[1] to acquire HEO/VEO
0: Disable reg 0x24[1] to acquire HEO/VEO
6 Reserved 1 RW
5 Reserved 0 RW
4 Reserved 0 RW
3 Reserved 0 RW
2 Reserved 0 RW
1 Reserved 0 RW
0 Reserved 0 RW
EOM_CNTL Reg 0x24 Channel 0x00 0x00 Eye Opening Monitor Control Register
7 fast_eom 0 RW 1: Enable Fast EOM mode
0: Disable fast EOM mode
6 Reserved 0 R
5 get_heo_veo_error_no_hits 0 R 1: No zero crossing in the eye diagram observed
0: Zero crossing in the eye diagram detected
4 get_heo_veo_error_no_opening 0 R 1: Eye diagram is completely closed
0: Open eye diagram detected
3 Reserved 0 R
2 Reserved 0 R
1 eom_get_heo_veo 0 RW Acquire HEO & VEO(self-clearing)
0 eom_start 0 R Starts EOM counter(self-clearing)
EOM_MSB Reg 0x25 Channel 0x00 Eye opening monitor hits(MSB)
7 eom_count[15] 0 RW MSBs of EOM counter
6 eom_count[14] 0 RW
5 eom_count[13] 0 RW
4 eom_count[12] 0 RW
3 eom_count[11] 0 RW
2 eom_count[10] 0 RW
1 eom_count[9] 0 RW
0 eom_count[8] 0 RW
EOM_LSB Reg 0x26 Channel 0x00 Eye opening monitor hits(LSB)
7 eom_count[7] 0 RW LSBs of EOM counter
6 eom_count[6] 0 RW
5 eom_count[5] 0 RW
4 eom_count[4] 0 RW
3 eom_count[3] 0 RW
2 eom_count[2] 0 RW
1 eom_count[1] 0 RW
0 eom_count[0] 0 RW
HEO Reg 0x27 Channel 0x00 Horizontal Eye Opening
7 heo[7] 0 R HEO value. This is measured in 0-63 phase settings. To get HEO in UI, read HEO, convert hex to dec, then divide by 64.
6 heo[6] 0 R
5 heo[5] 0 R
4 heo[4] 0 R
3 heo[3] 0 R
2 heo[2] 0 R
1 heo[1] 0 R
0 heo[0] 0 R
VEO Reg 0x28 Channel 0x00 Vertical Eye Opening
7 veo[7] 0 R This is measured in 0-63 vertical steps. To get VEO in mV, read VEO, convert hex to dec, then multiply by 3.125mV
6 veo[6] 0 R
5 veo[5] 0 R
4 veo[4] 0 R
3 veo[3] 0 R
2 veo[2] 0 R
1 veo[1] 0 R
0 veo[0] 0 R
Auto_EOM _Vrange Reg 0x29 Channel 0x00 EOM Vrange Readback
7 Reserved 0 RW
6 eom_vrange_setting[1] 00 R Auto Vrange readback of eye monitor granularity
00: 3.125mV
01: 6.25mV
10: 9.375mV
11: 12.5mV
5 eom_vrange_setting[0]
4 Reserved 0 RW
3 Reserved 0 RW
2 Reserved 0 RW
1 Reserved 0 RW
0 Reserved 0 RW
EOM_Timer_Thr Reg 0x2A Channel 0x30 EOM Hit Timer
7 eom_timer_thr[7] 0 RW EOM timer for how long to check each phase/voltage setting
6 eom_timer_thr[6] 0 RW
5 eom_timer_thr[5] 1 RW
4 eom_timer_thr[4] 1 RW
3 eom_timer_thr[3] 0 RW
2 eom_timer_thr[2] 0 RW
1 eom_timer_thr[1] 0 RW
0 eom_timer_thr[0] 0 RW
VEO_Scale Reg 0x2C Channel 0x32 VEO_Scale
7 Reserved 0 RW
6 veo_scale 0 RW 1: Enable Auto VEO scaling
0: VEO scaling based on Vrange Setting (0x11[7:6])
5 Reserved 1 RW
4 Reserved 1 RW
3 Reserved 0 RW
2 Reserved 0 RW
1 Reserved 1 RW
0 Reserved 0 RW
Rate_Subrate Reg_0x2F Channel 0x06 SMPTE_10GbE Selection
7 RATE[1] 0 RW 00: SMPTE Enable
01: 10G Ethernet Enable
Other Settings - Invalid
6 RATE[0] 0 RW
5 Reserved 0 RW
4 Reserved 0 RW
3 Reserved 0 RW
2 Reserved 1 RW
1 Reserved 1 RW
0 Reserved 0 R
HEO VEO Threshold Reg 0x32 Channel 0x11 HEO/VEO Interrupt Threshold
7 heo_int_thresh[3] 0 RW Compares HEO value, 0x27[7:0], vs threshold 0x32[7:4] * 4
6 heo_int_thresh[2] 0 RW
5 heo_int_thresh[1] 0 RW
4 heo_int_thresh[0] 1 RW
3 veo_int_thresh[3] 0 RW Compares VEO value, 0x28[7:0], vs threshold 0x32[3:0 * 4
2 veo_int_thresh[2] 0 RW
1 veo_int_thresh[1] 0 RW
0 veo_int_thresh[0] 1 RW
CDR State Machine Control Reg 0x3E Channel 0x80 CDR State Machine Setting
7 Reserved 1 RW At power-up, this bit needs to be set to 0'b. See initialization set up
6 Reserved 0 RW
5 Reserved 0 RW
4 Reserved 0 RW
3 Reserved 0 RW
2 Reserved 0 RW
1 Reserved 0 RW
0 Reserved 0 RW
HEO_VEO_Lock Reg 0x69 Channel 0x0A HEO/VEO Interval Monitoring
7 Reserved 0 RW
6 Reserved 0 RW
5 Reserved 0 RW
4 Reserved 0 RW
3 hv_lckmon_cnt_ms[3] 1 RW While monitoring lock, this sets the interval time. Each interval is 6.5 ms. At default condition, HEO_VEO Lock Monitor occurs once every 65 ms.
2 hv_lckmon_cnt_ms[2] 0 RW
1 hv_lckmon_cnt_ms[1] 1 RW
0 hv_lckmon_cnt_ms[0] 0 RW
CDR State Machine Control Reg 0x6A Channel 0x44 CDR State Machine Control
7 Reserved 0 RW At power-up, this register should be set to 0x00. See initialization set up
6 Reserved 1 RW
5 Reserved 0 RW
4 Reserved 0 RW
3 Reserved 0 RW
2 Reserved 1 RW
1 Reserved 0 RW
0 Reserved 0 RW
SMPTE_Rate_Enable Reg 0xA0 Channel 0x1f SMPTE_Data_Rate_Lock_Restriction
7 Reserved 0 RW
6 Reserved 0 RW
5 Reserved 0 RW
4 dvb_enable 1 RW 1: Enable CDR Lock to 270 Mbps
0: Disable CDR Lock to 270 Mbps. Note LMH1218 Programming Guide (SNLU174) for details
3 hd_enable 1 RW 1: Enable CDR Lock to 1.485/1.4835 Gbps
0: Disable CDR Lock to 1.485/1.4835 Gbps
2 3G_enable 1 RW 1: Enable CDR Lock to 2.97/2.967 Gbps
0: Disable CDR Lock to 2.97/2.967 Gbps
1 6G_enable 1 RW 1: Enable CDR Lock to 5.94/5.934 Gbps
0: Disable CDR Lock to 5.94/5.934 Gbps
0 12G_enable 1 RW 1: Enable CDR Lock to 11.88/11.868 Gbps
0: Disable CDR Lock to 11.88/11.868 Gbps