SNLS474E February   2015  – June 2018 LMH1218

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified SPI Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD
    2.     Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface AC Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Loss of Signal Detector
      2. 7.3.2 Continuous Time Linear Equalizer (CTLE)
      3. 7.3.3 2:1 Multiplexer
      4. 7.3.4 Clock and Data Recovery
      5. 7.3.5 Eye Opening Monitor (EOM)
      6. 7.3.6 Fast EOM
        1. 7.3.6.1 SMBus Fast EOM Operation
        2. 7.3.6.2 SPI Fast EOM Operation
      7. 7.3.7 LMH1218 Device Configuration
        1. 7.3.7.1 MODE_SEL
        2. 7.3.7.2 ENABLE
        3. 7.3.7.3 LOS_INT_N
        4. 7.3.7.4 LOCK
        5. 7.3.7.5 SMBus MODE
        6. 7.3.7.6 SMBus READ/WRITE Transaction
        7. 7.3.7.7 SPI Mode
          1. 7.3.7.7.1 SPI READ/WRITE Transaction
          2. 7.3.7.7.2 SPI Write Transaction Format
          3. 7.3.7.7.3 SPI Read Transaction Format
        8. 7.3.7.8 SPI Daisy Chain
          1. 7.3.7.8.1 SPI Daisy Chain Write Example
          2. 7.3.7.8.2 SPI Daisy Chain Write Read Example
            1. 7.3.7.8.2.1 SPI Daisy Chain Length of Daisy Chain Illustration
      8. 7.3.8 Power-On Reset
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 Global Registers
      2. 7.6.2 Receiver Registers
      3. 7.6.3 CDR Registers
      4. 7.6.4 Transmitter Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Guidance for All Applications
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
    4. 8.4 Initialization Set Up
      1. 8.4.1 Selective Data Rate Lock
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Solder Profile
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
PD Power dissipation Locked 75 Ω OUT0 only (800 mVpp), EOM powered down 300 mW
Locked OUT1 only (600 mVpp, diff), EOM powered down 195 mW
Transient power during CDR lock acquisition, 75 Ω OUT0 and OUT1 powered up, EOM powered down 400 500 mW
PD_RAW Power dissipation in force RAW mode (CDR bypass) EQ bypass, OUT0 720mVpp, OUT1 600mVpp
IN0 to OUT0 and OUT1 or IN1 to OUT0 and OUT1		 195 mW
IN0 to OUT0, OUT1 powered down 160 mW
IN1 to OUT1, OUT0 powered down 80 mW
4-LEVEL INPUT AND 2.5 V LVCMOS DC SPECIFICATIONS
VIH High level input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.95 × VDD V
VIF Float level input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.67 × VDD V
VI20K 20K to GND input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.33 × VDD V
VIL Low level input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.1 V
VOH High level output voltage IOH = -3 mA 2 V
VOL Low level output voltage IOL = 3 mA 0.4 V
IIH Input high leakage current Vinput = VDD
SPI Mode: LVCMOS (SPI_SCK, SPI_SS_N) pins		 15 µA
SMBus Mode: LVCMOS (SMB_SDA, SMB_SCL) pins 15 µA
SMBus Mode: 4-Levels (ADDR0, ADDR1) pins 20 44 80 µA
4-Levels (MODE_SEL, ENABLE) pins 20 44 80 µA
IIL Input low leakage current Vinput = GND
SPI Mode: LVCMOS (SPI_MOSI, SPI_SCK) pins		 –15 µA
Vinput = GND
SPI Mode: LVCMOS (SPI_SS_N) pins		 –37 µA
SMBus Mode: LVCMOS (SMB_SDA, SMB_SCL pins –15 µA
SMBus Mode: 4-Levels (ADDR0, ADDR1) pins –160 –93 –40 µA
4-Levels (MODE_SEL, ENABLE) pins –160 –93 –40 µA
3.3-V TOLERANT LVCMOS / LVTTL DC SPECIFICATIONS (SDA, SCL, LOS_INT_N)
VIH25 High level input voltage 2.5-V Supply Voltage 1.75 3.6 V
VIL Low level input voltage GND 0.8 V
VOL Low level output voltage IOL = 1.25 mA 0.4 V
IIH Input high current VIN = 2.5 V, VDD = 2.5 V 20 40 μA
IIL Input low current VIN = GND, VDD = 2.5 V -10 10 μA
SIGNALDETECT
SDH Signal detect (default)
Assert threshold level(2)(3) 		11.88 Gbps, SMPTE (EQ, PLL) Pathological Pattern 26 mVP-P
10.3125 Gbps, 1010 Clock Pattern, no media 30 mVP-P
10.3125 Gbps, PRBS31 Pattern 21 mVP-P
SDL Signal detect (default)
De-assert threshold level(2) 		11.88 Gbps, SMPTE (EQ, PLL) Pathological Patterns 20 mVP-P
10.3125 Gbps, 1010 Clock Pattern 15 mVP-P
10.3125 Gbps, PRBS31 Pattern 12 mVP-P
HIGH-SPEED RECEIVE RX INPUTS (IN_n+, IN_n–)
R_RD DC Input differential resistance 75 100 125 Ω
RLRX-SDD Input differential return loss(1) Measured with the device powered up.
SDD11 10 MHz to 2 GHz		 –14  dB
SDD11 2 GHz to 6 GHz –6.5  dB
SDD11 6 GHz to 12 GHz –6.5  dB
RLRX-SCD Differential to common mode Input conversion(1) Measure with the device powered up.SCD11, 10 MHz to 12 GHz  –20 dB
HIGH-SPEED OUTPUTS (OUT_n+, OUT_n–)
VVOD_OUT1 Output differential voltage(1)(5) Default setting, 8T clock pattern 400 600 700 mVP-P
VVOD_OUT1_DE De-emphasis Level VOD = 600 mV, maximum De-Emphasis with 16T clock pattern –9 dB
VVOD_OUT1_CLK Clock output differential voltage 2.97 GHz,1.485 GHz, 297 MHz, and 270 MHz 560 mVP-P
VVOD_OUT0 Output single ended voltage at OUT0+ with OUT0– terminated(1)(5)(9) Default setting 720 778 880 mVP-P
RDIFF_OUT1 DC output differential resistance 100 Ω
RDIFF_OUT0 DC output single-ended resistance 75 Ω
TR_F_OUT1 Output rise/fall time Full Slew Rate, 20% to 80% using 8T Pattern 45 ps
TR_F_OUT0 Output rise/fall time, PRBS10(1)(5) 11.88 Gbps 35 45 ps
5.94 Gbps 35 45 ps
2.97 Gbps 35 45 ps
1.485 Gbps 35 45 ps
270 Mbps 400 950 1500 ps
TR_F_OUT0_delta Output rise/fall time mismatch(1)(5) 11.88 Gbps 3 18 ps
5.94 Gbps 3 18 ps
2.97 Gbps 3 18 ps
1.485 Gbps 3 18 ps
270 Mbps 72 500 ps
VOVR_UDR_SHOOT Output overshoot, undershoot(1)(5) 12G/6G/3G/HD/SD
Measured with 8T pattern		 2.4% 3.4%
VDC_OFFSET DC offset(1) 12G/6G/3G/HD/SD ±0.2 V
VDC_WANDER DC wander(1) 12G/6G/3G/HD/SD EQ Pathological 20 mV
RLOUT0_S22 OUT0 single-ended 75-Ω return loss(1)(5)(7) S22 5 MHz to 1.485 GHz < –15 dB
S22 1.485 GHz to 3 GHz < –10 dB
S22 3 GHz to 6 GHz < –7 dB
S22 6 GHz to 12 GHz < –4 dB
RLOUT1_SDD22 OUT1 differential 100-Ω return loss(1)(5)(6) SDD22 10 MHz - 2 GHz –20  dB
SDD22 2 GHz - 6 GHz  –17 dB
SDD22 6 GHz - 11.1 GHz  –14 dB
RLOUT1_SCC22 OUT1 common-mode 50-Ω return loss(1)(5)(6) SCC22 10 MHz - 4.75 GHz –11 dB
SCC22 4.75 GHz - 11.1 GHz –12 dB
VVCM_OUT1_NOISE AC common-mode voltage noise(1)(5) VOD = 0.6 Vpp, DE = 0dB, PRBS31, 10.3125 Gbps 8 mVRMS
TRCK_LATENCY Latency reclocked Reclocked Data 1.5 UI +195 ps
TRAW_LATENCY Latency CDR bypass Raw Data 230 ps
TRANSMIT OUTPUT JITTER SPECIFICATIONS
AJ_OUT0 Alignment jitter(1)(5) OUT0, PRBS15, 11.88 Gbps 0.18 UI
TJ_OUT1 Total jitter (1E-12)(1)(5) OUT1, PRBS15 10.3125 Gbps 0.12 UI
RJ_OUT1 Random jitter (rms) OUT1, PRBS15, 10.3125 Gbps 0.38 psRMS
DJ_OUT1 Deterministic jitter OUT1, PRBS15, 10.3125 Gbps 7 psP-P
DJ_OUT1_RAW Deterministic jitter OUT1, RAW MODE (CDR bypass)
PRBS15, 11.88 Gbps, 35 inch FR4 trace, EQ=0x95, VID = 800mVpp		 25 psP-P
CLOCK DATA RECOVERY
DDATA_RATE ST-2082 (proposed)(8) 11.88, 11.868 Gbps
ST-2081 (proposed)(8) 5.94, 5.934 Gbps
SMPTE 424(8) 2.97, 2.967 Gbps
SMPTE 292(8) 1.485, 1.4835 Gbps
SMPTE 259M(8) 270 Mbps
10 GbE(8) 10.3125 Gbps
PPLL_BW PLL bandwidth at –3 dB Measured with 0.2UI SJ at 10.3125 Gbps 8 MHz
Measured with 0.2UI SJ at 11.88 Gbps 13 MHz
Measured with 0.2UI SJ at 5.94 Gbps 7 MHz
Measured with 0.2UI SJ at 2.97 Gbps 5 MHz
Measured with 0.2UI SJ at 1.485 Gbps 3 MHz
Measured with 0.2UI SJ at 270 Mbps 1 MHz
JTOL Total input jitter tolerance TJ = DJ + RJ + SJ,
DJ+RJ = 0.15 UI
SJ/PJ, low to high upward sweep (10 kHz to 80 MHz)		 0.65 UI
TLOCK Lock time(1)(4) From signal detected to the lock asserted, HEO/VEO lock monitor disable, same setting for 11.88G, 5.94G, 2.97G, 1.485G and 270-MHz data rates <5 ms
TTEMP_LOCK CDR lock with temperature ramp Temperature Lock Range, 5ºC per minute ramp up and down, –40ºC to 85ºC operating range 125 °C
(1) These limits are ensured by bench characterization and are not production tested.
(2) Data with extraordinarily long periods of high-frequency 1010 data, and for long, lossy channels, the signal amplitude at the input to the device may be severely attenuated by the channel and may fall below the signal detect assert and/or de-assert thresholds.
(3) The voltage noise on the receiver inputs which has an amplitude larger than the signal detect assert threshold may trigger a signal detect assert condition
(4) The total CDR lock time depends on number of rate settings enabled and application data rate
(5) Dependent on board layout. Characterization data was measured with LMH1218EVM evaluation board
(6) Measure with the device powered up and outputs a clock signal.
(7) Output return loss is dependent on board design, this is measured with the LMH1218EVM evaluation board
(8) Data rate tolerance is within ±1000 ppm
(9) ATE Production tested using DC method. Apply differential DC signal at the input and measure OUT0P amplitude. OUT0N terminated in 75 Ω.