SNLS474E February   2015  – June 2018 LMH1218

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified SPI Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD
    2.     Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface AC Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Loss of Signal Detector
      2. 7.3.2 Continuous Time Linear Equalizer (CTLE)
      3. 7.3.3 2:1 Multiplexer
      4. 7.3.4 Clock and Data Recovery
      5. 7.3.5 Eye Opening Monitor (EOM)
      6. 7.3.6 Fast EOM
        1. 7.3.6.1 SMBus Fast EOM Operation
        2. 7.3.6.2 SPI Fast EOM Operation
      7. 7.3.7 LMH1218 Device Configuration
        1. 7.3.7.1 MODE_SEL
        2. 7.3.7.2 ENABLE
        3. 7.3.7.3 LOS_INT_N
        4. 7.3.7.4 LOCK
        5. 7.3.7.5 SMBus MODE
        6. 7.3.7.6 SMBus READ/WRITE Transaction
        7. 7.3.7.7 SPI Mode
          1. 7.3.7.7.1 SPI READ/WRITE Transaction
          2. 7.3.7.7.2 SPI Write Transaction Format
          3. 7.3.7.7.3 SPI Read Transaction Format
        8. 7.3.7.8 SPI Daisy Chain
          1. 7.3.7.8.1 SPI Daisy Chain Write Example
          2. 7.3.7.8.2 SPI Daisy Chain Write Read Example
            1. 7.3.7.8.2.1 SPI Daisy Chain Length of Daisy Chain Illustration
      8. 7.3.8 Power-On Reset
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 Global Registers
      2. 7.6.2 Receiver Registers
      3. 7.6.3 CDR Registers
      4. 7.6.4 Transmitter Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Guidance for All Applications
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
    4. 8.4 Initialization Set Up
      1. 8.4.1 Selective Data Rate Lock
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Solder Profile
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Overview

The LMH1218 is a 11.88Gbps/5.94Gbps/2.97Gbps/1.485Gbps/0.27Gbps/10GbE multi-rate serial digital video data cable driver with integrated reclocker intended for equalizing, reclocking, and driving data compatible to the SMPTE standards, proposed ST-2081/2, and 10GbE specifications. It is a 2-input, 2-output single-core chip, enabling 1:2 fan-out or 2:1 MUX operation. Each input has a 100-Ω continuous time linear equalizer (CTLE) at the front-end, intended to compensate for loss over STP coax, fiber, or FR-4 backplane. OUT1 is a 100-Ω driver compatible to 10GbE SFF-8431 optical module requirements. The LMH1218 OUT0 is a 75-Ω cable driver compatible to the SMPTE and proposed ST-2081/2 requirements.

The referenceless Clock-and-Data Recovery (CDR) circuit selects between the two inputs based on user choice. The reclocked output can be driven to one or two outputs. One of the outputs supports 100-Ω differential cable connection, while the other output can drive a 75-Ω SMPTE specified cable while meeting transmitter requirements as specified in SMPTE standard. The LMH1218 locks to all required SDI data rates, including 270Mbps, 1.485 Gbps, 1.4835 Gbps, 2.97 Gbps, 2.967 Gbps, 5.94 Gbps, 5.934 Gbps, 11.88 Gbps, and 11.868 Gbps as well as 10.3125 Gbps. The LMH1218 is assembled in a 4 mm × 4 mm 24-pin QFN package. The chip can be programmed using SPI or SMBus interface.