SNAS669E September 2015 – April 2018 LMK03318
PRODUCTION DATA.
Input Clock Select
Bit # | Field | Type | Reset | EEPROM | Description | |
---|---|---|---|---|---|---|
[7:6] | SECBUFSEL[1:0] | RW | 0x2 | Y | Secondary Input Buffer Selection. SECBUFSEL configures the Secondary Input Buffer as follows. | |
SECBUFSEL | Mode | |||||
0 (0x0) | Single-ended Input | |||||
1 (0x1) | Differential Input | |||||
2 (0x2) | Crystal Input | |||||
3 (0x3) | Disabled | |||||
[5:4] | PRIBUFSEL[1:0] | RW | 0x1 | Y | Primary Input Buffer Selection. PRIBUFSEL configures the Primary Input Buffer as follows. | |
PRIBUFSEL | Mode | |||||
0 (0x0) | Single-ended Input | |||||
1 (0x1) | Differential Input | |||||
2 (0x2) | Disabled | |||||
3 (0x3) | Disabled | |||||
[3:2] | RSRVD | RW | 0x1 | Y | Reserved. | |
[1:0] | INSEL_PLL[1:0] | RW | 0x1 | Y | Reference Input Selection for PLL. INSEL_PLL Determines the input select for PLL as follows. | |
INSEL_PLL | Input Mode | |||||
0 (0x0) | Automatic, Primary is preferred. | |||||
1 (0x1) | Determined by external pin, REFSEL. | |||||
2 (0x2) | Primary Input Selected. | |||||
3 (0x3) | Secondary Input Selected. | |||||
When INSEL_PLL is equal to b01 the REFSEL pin determines the reference clock source for PLL as follows. | ||||||
REFSEL | PLL Reference Clock | |||||
0 | PLL Reference is Primary input | |||||
VIM | PLL Reference is Secondary input | |||||
1 | PLL Input MUX is set to Automatic Mode |