SNAS669E September   2015  – April 2018 LMK03318

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      LMK03318 Simplified Block Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Thermal Information
    6. 8.6  Electrical Characteristics - Power Supply
    7. 8.7  Pullable Crystal Characteristics (SECREF_P, SECREF_N)
    8. 8.8  Non-Pullable Crystal Characteristics (SECREF_P, SECREF_N)
    9. 8.9  Clock Input Characteristics (PRIREF_P/PRIREF_N, SECREF_P/SECREF_N)
    10. 8.10 VCO Characteristics
    11. 8.11 PLL Characteristics
    12. 8.12 1.8-V LVCMOS Output Characteristics (OUT[7:0])
    13. 8.13 LVCMOS Output Characteristics (STATUS[1:0])
    14. 8.14 Open-Drain Output Characteristics (STATUS[1:0])
    15. 8.15 AC-LVPECL Output Characteristics
    16. 8.16 AC-LVDS Output Characteristics
    17. 8.17 AC-CML Output Characteristics
    18. 8.18 HCSL Output Characteristics
    19. 8.19 Power-On Reset Characteristics
    20. 8.20 2-Level Logic Input Characteristics (HW_SW_CTRL, PDN, GPIO[5:0])
    21. 8.21 3-Level Logic Input Characteristics (REFSEL, GPIO[3:1])
    22. 8.22 Analog Input Characteristics (GPIO[5])
    23. 8.23 I2C-Compatible Interface Characteristics (SDA, SCL)
    24. 8.24 Typical 156.25-MHz Closed-Loop Output Phase Noise Characteristics
    25. 8.25 Typical 161.1328125-MHz Closed-Loop Output Phase Noise Characteristics
    26. 8.26 Closed-Loop Output Jitter Characteristics
    27. 8.27 PCIe Clock Output Jitter
    28. 8.28 Typical Power Supply Noise Rejection Characteristics
    29. 8.29 Typical Power-Supply Noise Rejection Characteristics
    30. 8.30 Typical Closed-Loop Output Spur Characteristics
    31. 8.31 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Test Configurations
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Device Block-Level Description
      2. 10.3.2 Device Configuration Control
        1. 10.3.2.1 Hard-Pin Mode (HW_SW_CTRL = 1)
          1. 10.3.2.1.1 PLL Block
          2. 10.3.2.1.2 Output Buffer Auto Mute
          3. 10.3.2.1.3 Input Block
          4. 10.3.2.1.4 Channel Mux
          5. 10.3.2.1.5 Output Divider
          6. 10.3.2.1.6 Output Driver Format
          7. 10.3.2.1.7 Status MUX, Divider and Slew Rate
        2. 10.3.2.2 Soft-Pin Programming Mode (HW_SW_CTRL = 0)
          1. 10.3.2.2.1 Device Config Space
          2. 10.3.2.2.2 PLL Block
          3. 10.3.2.2.3 Output Buffer Auto Mute
          4. 10.3.2.2.4 Input Block
          5. 10.3.2.2.5 Channel Mux
          6. 10.3.2.2.6 Output Divider
          7. 10.3.2.2.7 Output Driver Format
          8. 10.3.2.2.8 Status MUX, Divider and Slew Rate
        3. 10.3.2.3 Register File Reference Convention
    4. 10.4 Device Functional Modes
      1. 10.4.1  Smart Input MUX
      2. 10.4.2  Universal Input Buffer (PRI_REF, SEC_REF)
      3. 10.4.3  Crystal Input Interface (SEC_REF)
      4. 10.4.4  Reference Doubler
      5. 10.4.5  Reference Divider (R)
      6. 10.4.6  Input Divider (M)
      7. 10.4.7  Feedback Divider (N)
      8. 10.4.8  Phase Frequency Detector (PFD)
      9. 10.4.9  Charge Pump
      10. 10.4.10 Loop Filter
      11. 10.4.11 VCO Calibration
      12. 10.4.12 Fractional Circuitry
        1. 10.4.12.1 Programmable Dithering Levels
        2. 10.4.12.2 Programmable Delta Sigma Modulator Order
      13. 10.4.13 Post Divider
      14. 10.4.14 High-Speed Output MUX
      15. 10.4.15 High-Speed Output Divider
      16. 10.4.16 High-Speed Clock Outputs
      17. 10.4.17 Output Synchronization
      18. 10.4.18 Status Outputs
        1. 10.4.18.1 Loss of Reference
        2. 10.4.18.2 Loss of Lock
    5. 10.5 Programming
      1. 10.5.1 I2C Serial Interface
      2. 10.5.2 Block Register Write
      3. 10.5.3 Block Register Read
      4. 10.5.4 Write SRAM
      5. 10.5.5 Write EEPROM
      6. 10.5.6 Read SRAM
      7. 10.5.7 Read EEPROM
      8. 10.5.8 Read ROM
      9. 10.5.9 Default Device Configurations in EEPROM and ROM
    6. 10.6 Register Maps
      1. 10.6.1   VNDRID_BY1 Register; R0
      2. 10.6.2   VNDRID_BY0 Register; R1
      3. 10.6.3   PRODID Register; R2
      4. 10.6.4   REVID Register; R3
      5. 10.6.5   PARTID Register; R4
      6. 10.6.6   PINMODE_SW Register; R8
      7. 10.6.7   PINMODE_HW Register; R9
      8. 10.6.8   SLAVEADR Register; R10
      9. 10.6.9   EEREV Register; R11
      10. 10.6.10  DEV_CTL Register; R12
      11. 10.6.11  INT_LIVE Register; R13
      12. 10.6.12  INT_MASK Register; R14
      13. 10.6.13  INT_FLAG_POL Register; R15
      14. 10.6.14  INT_FLAG Register; R16
      15. 10.6.15  INTCTL Register; R17
      16. 10.6.16  OSCCTL2 Register; R18
      17. 10.6.17  STATCTL Register; R19
      18. 10.6.18  MUTELVL1 Register; R20
      19. 10.6.19  MUTELVL2 Register; R21
      20. 10.6.20  OUT_MUTE Register; R22
      21. 10.6.21  STATUS_MUTE Register; R23
      22. 10.6.22  DYN_DLY Register; R24
      23. 10.6.23  REFDETCTL Register; R25
      24. 10.6.24  STAT0_INT Register; R27
      25. 10.6.25  STAT1 Register; R28
      26. 10.6.26  OSCCTL1 Register; R29
      27. 10.6.27  PWDN Register; R30
      28. 10.6.28  OUTCTL_0 Register; R31
      29. 10.6.29  OUTCTL_1 Register; R32
      30. 10.6.30  OUTDIV_0_1 Register; R33
      31. 10.6.31  OUTCTL_2 Register; R34
      32. 10.6.32  OUTCTL_3 Register; R35
      33. 10.6.33  OUTDIV_2_3 Register; R36
      34. 10.6.34  OUTCTL_4 Register; R37
      35. 10.6.35  OUTDIV_4 Register; R38
      36. 10.6.36  OUTCTL_5 Register; R39
      37. 10.6.37  OUTDIV_5 Register; R40
      38. 10.6.38  OUTCTL_6 Register; R41
      39. 10.6.39  OUTDIV_6 Register; R42
      40. 10.6.40  OUTCTL_7 Register; R43
      41. 10.6.41  OUTDIV_7 Register; R44
      42. 10.6.42  CMOSDIVCTRL Register; R45
      43. 10.6.43  CMOSDIV0 Register; R46
      44. 10.6.44  STATUS_SLEW Register; R49
      45. 10.6.45  IPCLKSEL Register; R50
      46. 10.6.46  IPCLKCTL Register; R51
      47. 10.6.47  PLL_RDIV Register; R52
      48. 10.6.48  PLL_MDIV Register; R53
      49. 10.6.49  PLL_CTRL0 Register; R56
      50. 10.6.50  PLL_CTRL1 Register; R57
      51. 10.6.51  PLL_NDIV_BY1 Register; R58
      52. 10.6.52  PLL_NDIV_BY0 Register; R59
      53. 10.6.53  PLL_FRACNUM_BY2 Register; R60
      54. 10.6.54  PLL_FRACNUM_BY1 Register; R61
      55. 10.6.55  PLL_FRACNUM_BY0 Register; R62
      56. 10.6.56  PLL_FRACDEN_BY2 Register; R63
      57. 10.6.57  PLL_FRACDEN_BY1 Register; R64
      58. 10.6.58  PLL_FRACDEN_BY0 Register; R65
      59. 10.6.59  PLL_MASHCTRL Register; R66
      60. 10.6.60  PLL_LF_R2 Register; R67
      61. 10.6.61  PLL_LF_C1 Register; R68
      62. 10.6.62  PLL_LF_R3 Register; R69
      63. 10.6.63  PLL_LF_C3 Register; R70
      64. 10.6.64  SEC_CTRL Register; R72
      65. 10.6.65  XO_MARGINING Register; R86
      66. 10.6.66  XO_OFFSET_GPIO5_STEP_1_BY1 Register; R88
      67. 10.6.67  XO_OFFSET_GPIO5_STEP_1_BY0 Register; R89
      68. 10.6.68  XO_OFFSET_GPIO5_STEP_2_BY1 Register; R90
      69. 10.6.69  XO_OFFSET_GPIO5_STEP_2_BY0 Register; R91
      70. 10.6.70  XO_OFFSET_GPIO5_STEP_3_BY1 Register; R92
      71. 10.6.71  XO_OFFSET_GPIO5_STEP_3_BY0 Register; R93
      72. 10.6.72  XO_OFFSET_GPIO5_STEP_4_BY1 Register; R94
      73. 10.6.73  XO_OFFSET_GPIO5_STEP_4_BY0 Register; R95
      74. 10.6.74  XO_OFFSET_GPIO5_STEP_5_BY1 Register; R96
      75. 10.6.75  XO_OFFSET_GPIO5_STEP_5_BY0 Register; R97
      76. 10.6.76  XO_OFFSET_GPIO5_STEP_6_BY1 Register; R98
      77. 10.6.77  XO_OFFSET_GPIO5_STEP_6_BY0 Register; R99
      78. 10.6.78  XO_OFFSET_GPIO5_STEP_7_BY1 Register; R100
      79. 10.6.79  XO_OFFSET_GPIO5_STEP_7_BY0 Register; R101
      80. 10.6.80  XO_OFFSET_GPIO5_STEP_8_BY1 Register; R102
      81. 10.6.81  XO_OFFSET_GPIO5_STEP_8_BY0 Register; R103
      82. 10.6.82  XO_OFFSET_SW_BY1 Register; R104
      83. 10.6.83  XO_OFFSET_SW_BY0 Register; R105
      84. 10.6.84  PLL_CTRL2 Register; R117
      85. 10.6.85  PLL_CTRL3 Register; R118
      86. 10.6.86  PLL_CALCTRL0 Register; R119
      87. 10.6.87  PLL_CALCTRL1 Register; R120
      88. 10.6.88  NVMCNT Register; R136
      89. 10.6.89  NVMCTL Register; R137
      90. 10.6.90  NVMLCRC Register; R138
      91. 10.6.91  MEMADR_BY1 Register; R139
      92. 10.6.92  MEMADR_BY0 Register; R140
      93. 10.6.93  NVMDAT Register; R141
      94. 10.6.94  RAMDAT Register; R142
      95. 10.6.95  ROMDAT Register; R143
      96. 10.6.96  NVMUNLK Register; R144
      97. 10.6.97  REGCOMMIT_PAGE Register; R145
      98. 10.6.98  XOCAPCTRL_BY1 Register; R199
      99. 10.6.99  XOCAPCTRL_BY0 Register; R200
      100. 10.6.100 EEPROM Map
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Application Block Diagram Examples
      2. 11.2.2 Jitter Considerations in Serdes Systems
      3. 11.2.3 Frequency Margining
        1. 11.2.3.1 Fine Frequency Margining
        2. 11.2.3.2 Coarse Frequency Margining
      4. 11.2.4 Design Requirements
        1. 11.2.4.1 Detailed Design Procedure
          1. 11.2.4.1.1 Device Selection
            1. 11.2.4.1.1.1 Calculation Using LCM
          2. 11.2.4.1.2 Device Configuration
          3. 11.2.4.1.3 PLL Loop Filter Design
            1. 11.2.4.1.3.1 PLL Loop Filter Design
          4. 11.2.4.1.4 Clock Output Assignment
        2. 11.2.4.2 Spur Mitigation Techniques
          1. 11.2.4.2.1 Phase Detector Spurs
          2. 11.2.4.2.2 Integer Boundary Fractional Spurs
          3. 11.2.4.2.3 Primary Fractional Spurs
          4. 11.2.4.2.4 Sub-Fractional Spurs
  12. 12Power Supply Recommendations
    1. 12.1 Device Power Up Sequence
    2. 12.2 Device Power Up Timing
    3. 12.3 Power Down
    4. 12.4 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
      1. 12.4.1 Mixing Supplies
      2. 12.4.2 Power-On Reset
      3. 12.4.3 Powering Up From Single-Supply Rail
      4. 12.4.4 Powering Up From Split-Supply Rails
      5. 12.4.5 Slow Power-Up Supply Ramp
      6. 12.4.6 Non-Monotonic Power-Up Supply Ramp
      7. 12.4.7 Slow Reference Input Clock Startup
    5. 12.5 Power Supply Bypassing
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Ensure Thermal Reliability
      2. 13.1.2 Support for PCB Temperature up to 105°C
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Third-Party Products Disclaimer
    2. 14.2 Receiving Notification of Documentation Updates
    3. 14.3 Community Resources
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.6 Register Maps

The register map is shown in the table below. The registers occupy a single unified address space and all registers are accessible at any time. A total of 103 registers are present in the LMK03318.

Name Address Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
VNDRID_BY1 0 0x10 VNDRID[15:8]
VNDRID_BY0 1 0x0B VNDRID[7:0]
PRODID 2 0x33 PRODID[7:0]
REVID 3 0x02 REVID[7:0]
PARTID 4 0x01 PRTID[7:0]
PINMODE_SW 8 0x00 HW_SW_CTRL_MODE GPIO32_SW_MODE[2:0] RSRVD
PINMODE_HW 9 0x00 GPIO_HW_MODE[5:0] RSRVD
SLAVEADR 10 0x50 SLAVEADR_GPIO1_SW[7:1] RSRVD
EEREV 11 0x00 EEREV[7:0]
DEV_CTL 12 0xD9 RESETN_SW SYNCN_SW RSRVD SYNC_AUTO SYNC_MUTE AONAFTER
LOCK		 PLLSTRTMODE AUTOSTRT
INT_LIVE 13 0x00 LOL LOS CAL RSRVD SECTOPRI RSRVD
INT_MASK 14 0x00 LOL_MASK LOS_MASK CAL_MASK RSRVD SECTOPRI_ MASK RSRVD
INT_FLAG_POL 15 0x00 LOL_POL LOS_POL CAL_POL RSRVD SECTOPRI_ POL RSRVD
INT_FLAG 16 0x00 LOL_INTR LOS_INTR CAL_INTR RSRVD SECTOPRI_ INTR RSRVD
INTCTL 17 0x00 RSRVD INT_AND_OR INT_EN
OSCCTL2 18 0x00 RISE_VALID_
SEC		 FALL_VALID_
SEC		 RISE_VALID_
PRI		 FALL_VALID_
PRI		 RSRVD
STATCTL 19 0x00 RSRVD STAT1_SHOOT_THRU_LIMIT STAT0_SHOOT_THRU_LIMIT RSRVD STAT1_OPEND STAT0_OPEND
MUTELVL1 20 0x55 CH3_MUTE_LVL[1:0] CH2_MUTE_LVL[1:0] CH1_MUTE_LVL[1:0] CH0_MUTE_LVL[1:0]
MUTELVL2 21 0x55 CH7_MUTE_LVL[1:0] CH6_MUTE_LVL[1:0] CH5_MUTE_LVL[1:0] CH4_MUTE_LVL[1:0]
OUT_MUTE 22 0xFF CH_7_MUTE CH_6_MUTE CH_5_MUTE CH_4_MUTE CH_3_MUTE CH_2_MUTE CH_1_MUTE CH_0_MUTE
STATUS_MUTE 23 0x02 RSRVD STATUS1_
MUTE		 STATUS0_
MUTE
DYN_DLY 24 0x00 RSRVD DIV_7_DYN_
DLY		 DIV_6_DYN_
DLY		 DIV_5_DYN_
DLY		 DIV_4_DYN_
DLY		 DIV_23_DYN_
DLY		 DIV_01_DYN_
DLY
REFDETCTL 25 0x55 DETECT_MODE_SEC[1:0] DETECT_MODE_PRI[1:0] LVL_SEL_SEC[1:0] LVL_SEL_PRI[1:0]
STAT0_INT 27 0x58 STAT0_SEL[3:0] STAT0_POL RSRVD
STAT1 28 0x28 STAT1_SEL[3:0] STAT1_POL RSRVD
OSCCTL1 29 0x06 DETECT_BYP RSRVD TERM2GND_
SEC		 TERM2GND_
PRI		 DIFFTERM_SEC DIFFTERM_PRI AC_MODE_SEC AC_MODE_PRI
PWDN 30 0x00 RSRVD CMOSCHPWDN CH7PWDN CH6PWDN CH5PWDN CH4PWDN CH23PWDN CH01PWDN
OUTCTL_0 31 0xB0 RSRVD OUT_0_SEL[1:0] OUT_0_MODE1[1:0] OUT_0_MODE2[1:0] RSRVD
OUTCTL_1 32 0x30 RSRVD OUT_1_SEL[1:0] OUT_1_MODE1[1:0] OUT_1_MODE2[1:0] RSRVD
OUTDIV_0_1 33 0x01 OUT_0_1_DIV[7:0]
OUTCTL_2 34 0xB0 RSRVD OUT_2_SEL[1:0] OUT_2_MODE1[1:0] OUT_2_MODE2[1:0] RSRVD
OUTCTL_3 35 0x30 RSRVD OUT_3_SEL[1:0] OUT_3_MODE1[1:0] OUT_3_MODE2[1:0] RSRVD
OUTDIV_2_3 36 0x03 OUT_2_3_DIV[7:0]
OUTCTL_4 37 0x18 CH_4_MUX[1:0] OUT_4_SEL[1:0] OUT_4_MODE1[1:0] OUT_4_MODE2[1:0]
OUTDIV_4 38 0x02 OUT_4_DIV[7:0]
OUTCTL_5 39 0x18 CH_5_MUX[1:0] OUT_5_SEL[1:0] OUT_5_MODE1[1:0] OUT_5_MODE2[1:0]
OUTDIV_5 40 0x02 OUT_5_DIV[7:0]
OUTCTL_6 41 0x18 CH_6_MUX[1:0] OUT_6_SEL[1:0] OUT_6_MODE1[1:0] OUT_6_MODE2[1:0]
OUTDIV_6 42 0x05 OUT_6_DIV[7:0]
OUTCTL_7 43 0x18 CH_7_MUX[1:0] OUT_7_SEL[1:0] OUT_7_MODE1[1:0] OUT_7_MODE2[1:0]
OUTDIV_7 44 0x05 OUT_7_DIV[7:0]
CMOSDIVCTRL 45 0x0A RSRVD PLLCMOSPREDIV[1:0] STATUS1MUX[1:0] STATUS0MUX[1:0]
CMOSDIV0 46 0x00 CMOSDIV0[7:0]
STATUS_SLEW 49 0x00 RSRVD STATUS1SLEW[1:0] STATUS0SLEW[1:0]
IPCLKSEL 50 0x95 SECBUFSEL[1:0] PRIBUFSEL[1:0] RSRVD INSEL_PLL[1:0]
IPCLKCTL 51 0x03 CLKMUX_
BYPASS		 RSRVD SECONSWITCH SECBUFGAIN PRIBUFGAIN
PLL_RDIV 52 0x00 RSRVD PLLRDIV[2:0]
PLL_MDIV 53 0x00 RSRVD PLLMDIV[4:0]
PLL_CTRL0 56 0x1E RSRVD PLL_P[2:0] PLL_SYNC_EN PLL_PDN
PLL_CTRL1 57 0x18 RSRVD PRI_D PLL_CP[3:0]
PLL_NDIV_BY1 58 0x00 RSRVD PLL_NDIV[11:8]
PLL_NDIV_BY0 59 0x66 PLL_NDIV[7:0]
PLL_
FRACNUM_BY2		 60 0x00 RSRVD PLL_NUM[21:16]
PLL_
FRACNUM_BY1		 61 0x00 PLL_NUM[15:8]
PLL_
FRACNUM_BY0		 62 0x00 PLL_NUM[7:0]
PLL_
FRACDEN_BY2		 63 0x00 RSRVD PLL_DEN[21:16]
PLL_
FRACDEN_BY1		 64 0x00 PLL_DEN[15:8]
PLL_
FRACDEN_BY0		 65 0x00 PLL_DEN[7:0]
PLL_
MASHCTRL		 66 0x0C RSRVD PLL_DTHRMODE[1:0] PLL_ORDER[1:0]
PLL_LF_R2 67 0x24 RSRVD PLL_LF_R2[5:0]
PLL_LF_C1 68 0x00 RSRVD PLL_LF_C1[2:0]
PLL_LF_R3 69 0x00 RSRVD PLL_LF_R3[5:0] PLL_LF_INT_FRAC
PLL_LF_C3 70 0x00 RSRVD PLL_LF_C3[2:0]
SEC_CTRL 72 0x18 RSRVD SEC_D RSRVD
XO_MARGINING 86 0x00 RSRVD MARGIN_DIG_STEP[2:0] MARGIN_OPTION[1:0] RSRVD RSRVD
XO_OFFSET_
GPIO5_STEP_1_BY1		 88 0x00 RSRVD XOOFFSET_STEP1[9:8]
XO_OFFSET_
GPIO5_STEP_1_BY0		 89 0xDE XOOFFSET_STEP1[7:0]
XO_OFFSET_
GPIO5_STEP_2_BY1		 90 0x01 RSRVD XOOFFSET_STEP2[9:8]
XO_OFFSET_
GPIO5_STEP_2_BY0		 91 0x18 XOOFFSET_STEP2[7:0]
XO_OFFSET_
GPIO5_STEP_3_BY1		 92 0x01 RSRVD XOOFFSET_STEP3[9:8]
XO_OFFSET_
GPIO5_STEP_3_BY0		 93 0x4B XOOFFSET_STEP3[7:0]
XO_OFFSET_
GPIO5_STEP_4_BY1		 94 0x01 RSRVD XOOFFSET_STEP4[9:8]
XO_OFFSET_
GPIO5_STEP_4_BY0		 95 0x86 XOOFFSET_STEP4[7:0]
XO_OFFSET_
GPIO5_STEP_5_BY1		 96 0x01 RSRVD XOOFFSET_STEP5[9:8]
XO_OFFSET_
GPIO5_STEP_5_BY0		 97 0xBE XOOFFSET_STEP5[7:0]
XO_OFFSET_
GPIO5_STEP_6_BY1		 98 0x01 RSRVD XOOFFSET_STEP6[9:8]
XO_OFFSET_
GPIO5_STEP_6_BY0		 99 0xFE XOOFFSET_STEP6[7:0]
XO_OFFSET_
GPIO5_STEP_7_BY1		 100 0x02 RSRVD XOOFFSET_STEP7[9:8]
XO_OFFSET_
GPIO5_STEP_7_BY0		 101 0x47 XOOFFSET_STEP7[7:0]
XO_OFFSET_
GPIO5_STEP_8_BY1		 102 0x02 RSRVD XOOFFSET_STEP8[9:8]
XO_OFFSET_
GPIO5_STEP_8_BY0		 103 0x9E XOOFFSET_STEP8[7:0]
XO_OFFSET_
SW_BY1		 104 0x00 RSRVD XOOFFSET_SW[9:8]
XO_OFFSET_
SW_BY0		 105 0x00 XOOFFSET_SW[7:0]
PLL_CTRL2 117 0x00 PLL_STRETCH RSRVD
PLL_CTRL3 118 0x03 RSRVD PLL_DISABLE_4TH[2:0]
PLL_
CALCTRL0		 119 0x01 RSRVD PLL_CLSDWAIT[1:0] PLL_VCOWAIT[1:0]
PLL_
CALCTRL1		 120 0x00 RSRVD PLL_LOOPBW
NVMSCRC 135 0x00 NVMSCRC[7:0]
NVMCNT 136 0x00 NVMCNT[7:0]
NVMCTL 137 0x10 RSRVD REGCOMMIT NVMCRCERR NVMAUTOCRC NVMCOMMIT NVMBUSY RSRVD NVMPROG
NVMLCRC 138 0x00 NVMLCRC[7:0]
MEMADR_BY1 139 0x00 RSRVD MEMADR[11:8]
MEMADR_BY0 140 0x00 MEMADR[7:0]
NVMDAT 141 0x00 NVMDAT[7:0]
RAMDAT 142 0x00 RAMDAT[7:0]
ROMDAT 143 0x00 ROMDAT[7:0]
NVMUNLK 144 0x00 NVMUNLK[7:0]
REGCOMMIT_
PAGE		 145 0x00 RSRVD REGCOMMIT_PG[3:0]
XOCAPCTRL_
BY1		 199 0x00 RSRVD XO_CAP_CTRL[9:8]
XOCAPCTRL_
BY0		 200 0x00 XO_CAP_CTRL[7:0]