SNAS668D August   2015  – April 2018 LMK03328

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      LMK03328 Simplified Block Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Thermal Information
    6. 8.6  Electrical Characteristics - Power Supply
    7. 8.7  Pullable Crystal Characteristics (SECREF_P, SECREF_N)
    8. 8.8  Non-Pullable Crystal Characteristics (SECREF_P, SECREF_N)
    9. 8.9  Clock Input Characteristics (PRIREF_P/PRIREF_N, SECREF_P/SECREF_N)
    10. 8.10 VCO Characteristics
    11. 8.11 PLL Characteristics
    12. 8.12 1.8-V LVCMOS Output Characteristics (OUT[7:0])
    13. 8.13 LVCMOS Output Characteristics (STATUS[1:0]
    14. 8.14 Open-Drain Output Characteristics (STATUS[1:0])
    15. 8.15 AC-LVPECL Output Characteristics
    16. 8.16 AC-LVDS Output Characteristics
    17. 8.17 AC-CML Output Characteristics
    18. 8.18 HCSL Output Characteristics
    19. 8.19 Power-On/Reset Characteristics
    20. 8.20 2-Level Logic Input Characteristics (HW_SW_CTRL, PDN, GPIO[5:0])
    21. 8.21 3-Level Logic Input Characteristics (REFSEL, GPIO[3:1])
    22. 8.22 Analog Input Characteristics (GPIO[5])
    23. 8.23 I2C-Compatible Interface Characteristics (SDA, SCL)
    24. 8.24 Typical 156.25-MHz, Closed-Loop Output Phase Noise Characteristics
    25. 8.25 Typical 161.1328125-MHz, Closed-Loop Output Phase Noise Characteristics
    26. 8.26 Closed-Loop Output Jitter Characteristics
    27. 8.27 PCIe Clock Output Jitter
    28. 8.28 Typical Power Supply Noise Rejection Characteristics
    29. 8.29 Typical Power Supply Noise Rejection Characteristics
    30. 8.30 Typical Closed-Loop Output Spur Characteristics
    31. 8.31 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Test Configurations
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Device Block-Level Description
      2. 10.3.2 Device Configuration Control
        1. 10.3.2.1 Hard Pin Mode (HW_SW_CTRL = 1)
          1. 10.3.2.1.1 PLL Blocks
          2. 10.3.2.1.2 Output Buffer Auto Mute
          3. 10.3.2.1.3 Input Block
          4. 10.3.2.1.4 Channel Mux
          5. 10.3.2.1.5 Output Divider
          6. 10.3.2.1.6 Output Driver Format
          7. 10.3.2.1.7 Status MUX, Divider and Slew Rate
        2. 10.3.2.2 Soft Pin Programming Mode (HW_SW_CTRL = 0)
          1. 10.3.2.2.1 Device Config Space
          2. 10.3.2.2.2 PLL Blocks
          3. 10.3.2.2.3 Output Buffer Auto Mute
          4. 10.3.2.2.4 Input Block
          5. 10.3.2.2.5 Channel Mux
          6. 10.3.2.2.6 Output Divider
          7. 10.3.2.2.7 Output Driver Format
          8. 10.3.2.2.8 Status MUX, Divider and Slew Rate
        3. 10.3.2.3 Register File Reference Convention
    4. 10.4 Device Functional Modes
      1. 10.4.1  Smart Input MUX
      2. 10.4.2  Universal Input Buffer (PRI_REF, SEC_REF)
      3. 10.4.3  Crystal Input Interface (SEC_REF)
      4. 10.4.4  Reference Doubler
      5. 10.4.5  Reference Divider (R)
      6. 10.4.6  Input Divider (M)
      7. 10.4.7  Feedback Divider (N)
      8. 10.4.8  Phase Frequency Detector (PFD)
      9. 10.4.9  Charge Pump
      10. 10.4.10 Loop Filter
      11. 10.4.11 VCO Calibration
      12. 10.4.12 Fractional Circuitry
        1. 10.4.12.1 Programmable Dithering Levels
        2. 10.4.12.2 Programmable Delta Sigma Modulator Order
      13. 10.4.13 Post Divider
      14. 10.4.14 High-Speed Output MUX
      15. 10.4.15 High-Speed Output Divider
      16. 10.4.16 High-Speed Clock Outputs
      17. 10.4.17 Output Synchronization
      18. 10.4.18 Status Outputs
        1. 10.4.18.1 Loss of Reference
        2. 10.4.18.2 Loss of Lock
    5. 10.5 Programming
      1. 10.5.1 I2C Serial Interface
      2. 10.5.2 Block Register Write
      3. 10.5.3 Block Register Read
      4. 10.5.4 Write SRAM
      5. 10.5.5 Write EEPROM
      6. 10.5.6 Read SRAM
      7. 10.5.7 Read EEPROM
      8. 10.5.8 Read ROM
      9. 10.5.9 Default Device Configurations in EEPROM and ROM
    6. 10.6 Register Maps
      1. 10.6.1   VNDRID_BY1 Register; R0
      2. 10.6.2   VNDRID_BY0 Register; R1
      3. 10.6.3   PRODID Register; R2
      4. 10.6.4   REVID Register; R3
      5. 10.6.5   PARTID Register; R4
      6. 10.6.6   PINMODE_SW Register; R8
      7. 10.6.7   PINMODE_HW Register; R9
      8. 10.6.8   SLAVEADR Register; R10
      9. 10.6.9   EEREV Register; R11
      10. 10.6.10  DEV_CTL Register; R12
      11. 10.6.11  INT_LIVE Register; R13
      12. 10.6.12  INT_MASK Register; R14
      13. 10.6.13  INT_FLAG_POL Register; R15
      14. 10.6.14  INT_FLAG Register; R16
      15. 10.6.15  INTCTL Register; R17
      16. 10.6.16  OSCCTL2 Register; R18
      17. 10.6.17  STATCTL Register; R19
      18. 10.6.18  MUTELVL1 Register; R20
      19. 10.6.19  MUTELVL2 Register; R21
      20. 10.6.20  OUT_MUTE Register; R22
      21. 10.6.21  STATUS_MUTE Register; R23
      22. 10.6.22  DYN_DLY Register; R24
      23. 10.6.23  REFDETCTL Register; R25
      24. 10.6.24  STAT0_INT Register; R27
      25. 10.6.25  STAT1 Register; R28
      26. 10.6.26  OSCCTL1 Register; R29
      27. 10.6.27  PWDN Register; R30
      28. 10.6.28  OUTCTL_0 Register; R31
      29. 10.6.29  OUTCTL_1 Register; R32
      30. 10.6.30  OUTDIV_0_1 Register; R33
      31. 10.6.31  OUTCTL_2 Register; R34
      32. 10.6.32  OUTCTL_3 Register; R35
      33. 10.6.33  OUTDIV_2_3 Register; R36
      34. 10.6.34  OUTCTL_4 Register; R37
      35. 10.6.35  OUTDIV_4 Register; R38
      36. 10.6.36  OUTCTL_5 Register; R39
      37. 10.6.37  OUTDIV_5 Register; R40
      38. 10.6.38  OUTCTL_6 Register; R41
      39. 10.6.39  OUTDIV_6 Register; R42
      40. 10.6.40  OUTCTL_7 Register; R43
      41. 10.6.41  OUTDIV_7 Register; R44
      42. 10.6.42  CMOSDIVCTRL Register; R45
      43. 10.6.43  CMOSDIV0 Register; R46
      44. 10.6.44  CMOSDIV1 Register; R47
      45. 10.6.45  STATUS_SLEW Register; R49
      46. 10.6.46  IPCLKSEL Register; R50
      47. 10.6.47  IPCLKCTL Register; R51
      48. 10.6.48  PLL1_RDIV Register; R52
      49. 10.6.49  PLL1_MDIV Register; R53
      50. 10.6.50  PLL2_RDIV Register; R54
      51. 10.6.51  PLL2_MDIV Register; R55
      52. 10.6.52  PLL1_CTRL0 Register; R56
      53. 10.6.53  PLL1_CTRL1 Register; R57
      54. 10.6.54  PLL1_NDIV_BY1 Register; R58
      55. 10.6.55  PLL1_NDIV_BY0 Register; R59
      56. 10.6.56  PLL1_FRACNUM_BY2 Register; R60
      57. 10.6.57  PLL1_FRACNUM_BY1 Register; R61
      58. 10.6.58  PLL1_FRACNUM_BY0 Register; R62
      59. 10.6.59  PLL_FRACDEN_BY2 Register; R63
      60. 10.6.60  PLL1_FRACDEN_BY1 Register; R64
      61. 10.6.61  PLL1_FRACDEN_BY0 Register; R65
      62. 10.6.62  PLL1_MASHCTRL Register; R66
      63. 10.6.63  PLL1_LF_R2 Register; R67
      64. 10.6.64  PLL1_LF_C1 Register; R68
      65. 10.6.65  PLL1_LF_R3 Register; R69
      66. 10.6.66  PLL1_LF_C3 Register; R70
      67. 10.6.67  PLL2_CTRL0 Register; R71
      68. 10.6.68  PLL2_CTRL1 Register; R72
      69. 10.6.69  PLL2_NDIV_BY1 Register; R73
      70. 10.6.70  PLL2_NDIV_BY0 Register; R74
      71. 10.6.71  PLL2_FRACNUM_BY2 Register; R75
      72. 10.6.72  PLL2_FRACNUM_BY1 Register; R76
      73. 10.6.73  PLL2_FRACNUM_BY0 Register; R77
      74. 10.6.74  PLL2_FRACDEN_BY2 Register; R78
      75. 10.6.75  PLL2_FRACDEN_BY1 Register; R79
      76. 10.6.76  PLL2_FRACDEN_BY0 Register; R80
      77. 10.6.77  PLL2_MASHCTRL Register; R81
      78. 10.6.78  PLL2_LF_R2 Register; R82
      79. 10.6.79  PLL2_LF_C1 Register; R83
      80. 10.6.80  PLL2_LF_R3 Register; R84
      81. 10.6.81  PLL2_LF_C3 Register; R85
      82. 10.6.82  XO_MARGINING Register; R86
      83. 10.6.83  XO_OFFSET_GPIO5_STEP_1_BY1 Register; R88
      84. 10.6.84  XO_OFFSET_GPIO5_STEP_1_BY0 Register; R89
      85. 10.6.85  XO_OFFSET_GPIO5_STEP_2_BY1 Register; R90
      86. 10.6.86  XO_OFFSET_GPIO5_STEP_2_BY0 Register; R91
      87. 10.6.87  XO_OFFSET_GPIO5_STEP_3_BY1 Register; R92
      88. 10.6.88  XO_OFFSET_GPIO5_STEP_3_BY0 Register; R93
      89. 10.6.89  XO_OFFSET_GPIO5_STEP_4_BY1 Register; R94
      90. 10.6.90  XO_OFFSET_GPIO5_STEP_4_BY0 Register; R95
      91. 10.6.91  XO_OFFSET_GPIO5_STEP_5_BY1 Register; R96
      92. 10.6.92  XO_OFFSET_GPIO5_STEP_5_BY0 Register; R97
      93. 10.6.93  XO_OFFSET_GPIO5_STEP_6_BY1 Register; R98
      94. 10.6.94  XO_OFFSET_GPIO5_STEP_6_BY0 Register; R99
      95. 10.6.95  XO_OFFSET_GPIO5_STEP_7_BY1 Register; R100
      96. 10.6.96  XO_OFFSET_GPIO5_STEP_7_BY0 Register; R101
      97. 10.6.97  XO_OFFSET_GPIO5_STEP_8_BY1 Register; R102
      98. 10.6.98  XO_OFFSET_GPIO5_STEP_8_BY0 Register; R103
      99. 10.6.99  XO_OFFSET_SW_BY1 Register; R104
      100. 10.6.100 XO_OFFSET_SW_BY0 Register; R105
      101. 10.6.101 PLL1_CTRL2 Register; R117
      102. 10.6.102 PLL1_CTRL3 Register; R118
      103. 10.6.103 PLL1_CALCTRL0 Register; R119
      104. 10.6.104 PLL1_CALCTRL1 Register; R120
      105. 10.6.105 PLL2_CTRL2 Register; R131
      106. 10.6.106 PLL2_CTRL3 Register; R132
      107. 10.6.107 PLL2_CALCTRL0 Register; R133
      108. 10.6.108 PLL2_CALCTRL1 Register; R134
      109. 10.6.109 NVMCNT Register; R136
      110. 10.6.110 NVMCTL Register; R137
      111. 10.6.111 NVMLCRC Register; R138
      112. 10.6.112 MEMADR_BY1 Register; R139
      113. 10.6.113 MEMADR_BY0 Register; R140
      114. 10.6.114 NVMDAT Register; R141
      115. 10.6.115 RAMDAT Register; R142
      116. 10.6.116 ROMDAT Register; R143
      117. 10.6.117 NVMUNLK Register; R144
      118. 10.6.118 REGCOMMIT_PAGE Register; R145
      119. 10.6.119 XOCAPCTRL_BY1 Register; R199
      120. 10.6.120 XOCAPCTRL_BY0 Register; R200
    7. 10.7 EEPROM Map
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Application Block Diagram Examples
      2. 11.2.2 Jitter Considerations in Serdes Systems
      3. 11.2.3 Frequency Margining
        1. 11.2.3.1 Fine Frequency Margining
        2. 11.2.3.2 Coarse Frequency Margining
      4. 11.2.4 Design Requirements
        1. 11.2.4.1 Detailed Design Procedure
          1. 11.2.4.1.1 Device Selection
            1. 11.2.4.1.1.1 Calculation Using LCM
          2. 11.2.4.1.2 Device Configuration
          3. 11.2.4.1.3 PLL Loop Filter Design
            1. 11.2.4.1.3.1 PLL Loop Filter Design
          4. 11.2.4.1.4 PLL and Clock Output Assignment
      5. 11.2.5 Spur Mitigation Techniques
        1. 11.2.5.1 Phase Detector Spurs
        2. 11.2.5.2 Integer Boundary Fractional Spurs
        3. 11.2.5.3 Primary Fractional Spurs
        4. 11.2.5.4 Sub-Fractional Spurs
  12. 12Power Supply Recommendations
    1. 12.1 Device Power Up Sequence
    2. 12.2 Device Power Up Timing
    3. 12.3 Power Down
    4. 12.4 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
      1. 12.4.1 Mixing Supplies
      2. 12.4.2 Power-On Reset
      3. 12.4.3 Powering Up From Single-Supply Rail
      4. 12.4.4 Powering Up From Split-Supply Rails
      5. 12.4.5 Slow Power-Up Supply Ramp
      6. 12.4.6 Non-Monotonic Power-Up Supply Ramp
      7. 12.4.7 Slow Reference Input Clock Start-Up
    5. 12.5 Power Supply Bypassing
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Ensure Thermal Reliability
      2. 13.1.2 Support for PCB Temperature up to 105°C
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 Community Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.5.9 Default Device Configurations in EEPROM and ROM

Table 10 through Table 14 show the device default configurations stored in the on-chip EEPROM. Table 15 through Table 19. show the device default configurations stored in the on-chip ROM.

Table 10. Default EEPROM Contents (HW_SW_CTRL = "0") – Input and Status Configuration(1)(2)

GPIO[3:2] PRI INPUT (MHz) PRI TYPE PRI DOUBLER SEC INPUT (MHz) SEC TYPE XO INT LOAD (pF) SEC DOUBLER STATUS1 MUX STATUS0 MUX STATUS1 PREDIV STATUS1 DIV STATUS1 FREQ (MHz) STATUS1 RISE / FALL TIME (ns)
VIM, VIM 25 LVDS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
00 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
01 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
10 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOR_
PRI		 n/a n/a n/a n/a
11 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
(1) 100-Ω internal termination enabled (if applicable)
(2) Internal AC biasing enabled (if applicable)

Table 11. Default EEPROM Contents (HW_SW_CTRL = "0") – PLL1 Configuration(1)

GPIO[3:2] PLL1 INPUT MUX(2) PLL1 INPUT (MHz) PLL1 TYPE PLL1 R DIV PLL1 M DIV PLL1 N DIV PLL1 N DIV INT PLL1 N DIV NUM PLL1 N DIV DEN PLL1 FRAC ORDER PLL1 FRAC DITHER PLL1 VCO (MHz) PLL1 P DIV
VIM, VIM REFSEL 50 Clock Gen Integer 1 1 102 102 0 1 n/a Disabled 5100 8
00 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 4
01 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
10 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
11 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
(1) When PLL1 is set as an integer-based clock generator, external loop filter component, C2, should be 3.3 nF and loop bandwidth is around 400 kHz. When PLL1 is set as a fractional-based clock generator, external loop filter component, C2, should be 33 nF and loop bandwidth is around 400 kHz.
(2) Refer to Table 3 when entry is REFSEL.

Table 12. Default EEPROM Contents (HW_SW_CTRL = "0") – PLL2 Configuration(1)

GPIO[3:2] PLL2 INPUT MUX(2) PLL2 INPUT (MHz) PLL2 TYPE PLL2 R DIV PLL2 M DIV PLL2 N DIV PLL2 N DIV INT PLL2 N DIV NUM PLL2 N DIV DEN PLL2 FRAC ORDER PLL2 FRAC DITHER PLL2 VCO (MHz) PLL2 P DIV
VIM, VIM REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
00 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
01 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 8
10 REFSEL 50 Disabled 1 1 1 1 0 1 n/a n/a n/a 8
11 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 8
(1) When PLL2 is set as an integer-based clock generator, external loop filter component, C2, should be 3.3 nF and loop bandwidth is around 400 kHz. When PLL2 is set as a fractional-based clock generator, external loop filter component, C2, should be 33 nF and loop bandwidth is around 400 kHz.
(2) Refer to Table 3 when entry is REFSEL.

Table 13. Default EEPROM Contents (HW_SW_CTRL = "0") – Outputs [0-3] Configuration

GPIO[3:2] OUT0-1 DIVIDER OUT0-1 FREQ (MHz) OUT0-1 MUX SELECT OUT0 TYPE OUT1 TYPE OUT2-3 DIVIDER OUT2-3 FREQ (MHz) OUT2-3 MUX SELECT OUT2 TYPE OUT3 TYPE
VIM, VIM 2 312.5 PLL2 LVPECL LVPECL 4 156.25 PLL2 LVPECL LVPECL
00 4 156.25 PLL2 LVPECL LVPECL 5 125 PLL2 LVPECL LVPECL
01 16 156.25 PLL1 LVPECL LVPECL 25 100 PLL2 LVPECL LVPECL
10 16 156.25 PLL1 LVPECL LVPECL 16 156.25 PLL1 LVPECL LVPECL
11 4 156.25 PLL1 LVPECL LVPECL 4 156.25 PLL1 LVPECL LVPECL

Table 14. Default EEPROM Contents (HW_SW_CTRL = "0") – Outputs [4-7] Configuration

GPIO [3:2] OUT4 DIV OUT4 FREQ (MHz) OUT4 MUX SELECT OUT4 TYPE OUT5 DIV OUT5 FREQ (MHz) OUT5 MUX SELECT OUT5 TYPE OUT6 DIV OUT6 FREQ (MHz) OUT6 MUX SELECT OUT6 TYPE OUT7 DIV OUT7 FREQ (MHz) OUT7 MUX SELECT OUT7 TYPE
VIM, VIM 3 212.5 PLL1 LVPECL 3 212.5 PLL1 LVPECL 6 106.25 PLL1 LVPECL 6 106.25 PLL1 LVPECL
00 48 25 PLL1 LVPECL 12 100 PLL1 LVPECL 1 n/a n/a Disable 18 66.6666 PLL1 LVCMOS
01 50 50 PLL2 LVPECL 20 125 PLL1 LVPECL 25 100 PLL2 LVCMOS 100 25 PLL2 LVCMOS
10 16 156.25 PLL1 LVPECL 16 156.25 PLL1 LVPECL 16 156.25 PLL1 LVPECL 16 156.25 PLL1 LVPECL
11 6 100 PLL2 LVPECL 24 25 PLL2 LVPECL 24 25 PLL2 LVPECL 6 100 PLL2 LVPECL

Table 15. Default ROM Contents (HW_SW_CTRL = "1") - Input and Status Configuration

GPIO[5:0] (decimal) PRI INPUT (MHz) PRI TYPE PRI DOUBLER SEC INPUT (MHz) SEC TYPE XO INT LOAD (pF) SEC DOUBLER STATUS1 MUX STATUS0 MUX STATUS1 PREDIV STATUS1 DIV STATUS1 FREQ (MHz) STATUS1 RISE / FALL TIME (ns)
0 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOR_PRI n/a n/a n/a n/a
1 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOR_PRI n/a n/a n/a n/a
2 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOR_PRI n/a n/a n/a n/a
3 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOR_PRI n/a n/a n/a n/a
4 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
5 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
6 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
7 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOR_PRI n/a n/a n/a n/a
8 25 LVCMOS Enabled 25 XTAL 9 Enabled PLL1 LOL1 5 15 66.6666 2.1
9 19.2 LVCMOS Enabled 19.2 LVCMOS n/a Enabled LOL1 LOL2 n/a n/a n/a n/a
10 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
11 38.88 LVCMOS Enabled 38.88 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
12 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
13 25 LVCMOS Enabled 25 XTAL 9 Enabled PLL1 LOL1 5 15 66.6666 2.1
14 25 LVCMOS Enabled 25 XTAL 9 Enabled PLL1 LOL1 5 15 66.6666 2.1
15 25 LVCMOS Enabled 25 XTAL 9 Enabled PLL1 LOL1 5 15 66.6666 LVCMOS
16 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
17 38.88 LVCMOS Enabled 38.88 LVCMOS n/a Enabled LOL1 LOR_PRI n/a n/a n/a n/a
18 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
19 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
20 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOR_PRI n/a n/a n/a n/a
21 25 LVCMOS Enabled 25 XTAL 9 Enabled PLL1 LOL1 5 15 66.6666 2.1
22 25 LVCMOS Enabled 25 XTAL 9 Enabled PLL1 LOL1 5 15 66.6666 2.1
23 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
24 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
25 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
26 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOR_PRI n/a n/a n/a n/a
27 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
28 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOR_PRI n/a n/a n/a n/a
29 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOR_PRI n/a n/a n/a n/a
30 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
31 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
32 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
33 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
34 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
35 25 LVCMOS Enabled 25 XTAL 9 Enabled PLL1 LOL1 5 15 66.6666 2.1
36 38.88 LVCMOS Enabled 38.88 LVCMOS n/a Enabled PLL1 LOL1 5 15 66.6666 2.1
37 19.2 LVCMOS Enabled 19.2 LVCMOS n/a Enabled PLL1 LOL1 5 15 66.6666 2.1
38 25 LVCMOS Enabled 25 LVCMOS n/a Enabled LOL1 LOL2 n/a n/a n/a n/a
39 25 LVCMOS Enabled 25 LVCMOS n/a Enabled LOL1 LOL2 n/a n/a n/a n/a
40 40.96 LVCMOS Enabled 40.96 LVCMOS n/a Enabled LOL1 LOL2 n/a n/a n/a n/a
41 25 LVCMOS Enabled 25 LVCMOS n/a Enabled LOL1 LOL2 n/a n/a n/a n/a
42 40.96 LVCMOS Enabled 40.96 LVCMOS n/a Enabled LOL1 LOL2 n/a n/a n/a n/a
43 25 LVCMOS Enabled 25 LVCMOS n/a Enabled LOL1 LOL2 n/a n/a n/a n/a
44 40.96 LVCMOS Enabled 40.96 LVCMOS n/a Enabled LOL1 LOL2 n/a n/a n/a n/a
45 27 LVCMOS Enabled 27 LVCMOS n/a Enabled LOL1 LOL2 n/a n/a n/a n/a
46 27 LVCMOS Enabled 27 LVCMOS n/a Enabled LOL1 LOL2 n/a n/a n/a n/a
47 25 LVCMOS Enabled 25 XTAL 9 Enabled PLL1 LOL1 5 15 66.6666 2.1
48 38.88 LVCMOS Enabled 38.88 XTAL 9 Enabled PLL1 LOL1 5 15 66.6666 2.1
49 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
50 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
51 112 LVCMOS Disabled 38.88 LVCMOS n/a Enabled LOL1 LOL2 n/a n/a n/a n/a
52 112 LVCMOS Disabled 38.88 LVCMOS n/a Enabled LOL1 LOL2 n/a n/a n/a n/a
53 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
54 38.88 LVCMOS Enabled 38.88 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
55 38.88 LVCMOS Enabled 38.88 LVCMOS n/a Enabled LOL1 LOR_PRI n/a n/a n/a n/a
56 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
57 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
58 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
59 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
60 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
61 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOR_PRI n/a n/a n/a n/a
62 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a
63 38.88 LVCMOS Enabled 38.88 XTAL 9 Enabled LOL1 LOL2 n/a n/a n/a n/a

Table 16. Default ROM Contents (HW_SW_CTRL = "1") - PLL1 Configuration(1)

GPIO[5:0] (decimal) PLL1 INPUT MUX(2) PLL1 INPUT (MHz) PLL1 TYPE PLL1 R DIV PLL1 M DIV PLL1 N DIV PLL1 N DIV INT PLL1 N DIV NUM PLL1 N DIV DEN PLL1 FRAC ORDER PLL1 FRAC DITHER PLL1 VCO (MHz) PLL1 P DIV
0 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
1 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
2 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
3 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 5
4 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
5 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
6 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
7 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 5
8 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
9 REFSEL 38.4 Clock Gen Fractional 1 1 128 128 0 1 n/a Disabled 4915.2 8
10 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 8
11 REFSEL 77.76 Clock Gen Fractional 1 1 64.30041165 64 1173483 3906250 Third Enabled 5000 2
12 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
13 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
14 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
15 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
16 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 8
17 REFSEL 77.76 Clock Gen Integer 1 1 64 64 0 1 n/a Disabled 4976.64 8
18 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 4
19 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
20 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
21 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
22 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
23 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
24 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
25 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
26 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
27 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
28 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
29 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
30 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
31 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
32 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
33 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 8
34 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
35 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
36 REFSEL 77.76 Clock Gen Fractional 1 1 64.30041165 64 1173483 3906250 Third Enabled 5000 8
37 REFSEL 38.4 Clock Gen Fractional 1 1 130.2083333 130 781250 3750000 Third Enabled 5000 8
38 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
39 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 4
40 REFSEL 81.92 Clock Gen Fractional 1 1 61.03515625 61 55296 1572864 Third Enabled 5000 4
41 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
42 REFSEL 81.92 Clock Gen Fractional 1 1 61.03515625 61 55296 1572864 Third Enabled 5000 8
43 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
44 REFSEL 81.92 Clock Gen Fractional 1 1 61.03515625 61 55296 1572864 Third Enabled 5000 8
45 REFSEL 54 Clock Gen Fractional 1 1 92.5925926 92 2370371 4000001 Third Enabled 5000 5
46 REFSEL 54 Clock Gen Fractional 1 1 92.16 92 640000 4000000 Third Enabled 4976.64 8
47 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
48 REFSEL 77.76 Clock Gen Fractional 1 1 64.30041165 64 1173483 3906250 Third Enabled 5000 2
49 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 2
50 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
51 SEC 77.76 Clock Gen Fractional 1 1 64.30041165 64 1173483 3906250 Third Enabled 5000 8
52 SEC 77.76 Clock Gen Fractional 1 1 64.30041165 64 1173483 3906250 Third Enabled 5000 8
53 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 5
54 REFSEL 77.76 Clock Gen Fractional 1 1 64.30041165 64 1173483 3906250 Third Enabled 5000 2
55 REFSEL 77.76 Clock Gen Fractional 1 1 64.30041165 64 1173483 3906250 Third Enabled 5000 8
56 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
57 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
58 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
59 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
60 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
61 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
62 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
63 REFSEL 77.76 Clock Gen Fractional 1 1 64.30041165 64 1173483 3906250 Third Enabled 5000 2
(1) When PLL1 is set as an integer-based clock generator, external loop filter component, C2, should be 3.3nF and loop bandwidth is around 400kHz. When PLL1 is set as a fractional-based clock generator, external loop filter component, C2, should be 33nF and loop bandwidth is around 400kHz.
(2) Refer to Table 3 when entry is REFSEL.

Table 17. Default ROM Contents (HW_SW_CTRL = "1") – PLL2 Configuration(1)

GPIO[5:0] (decimal) PLL2 INPUT MUX(2) PLL2 INPUT (MHz) PLL2 TYPE PLL2 R DIV PLL2 M DIV PLL2 N DIV PLL2 N DIV INT PLL2 N DIV NUM PLL2 N DIV DEN PLL2 FRAC ORDER PLL2 FRAC DITHER PLL2 VCO (MHz) PLL2 P DIV
0 REFSEL 50 Disabled 1 1 1 1 0 1 n/a n/a n/a 8
1 REFSEL 50 Disabled 1 1 1 1 0 1 n/a n/a n/a 8
2 REFSEL 50 Disabled 1 1 1 1 0 1 n/a n/a n/a 8
3 REFSEL 50 Disabled 1 1 1 1 0 1 n/a n/a n/a 8
4 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
5 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
6 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
7 REFSEL 50 Disabled 1 1 1 1 0 1 n/a n/a n/a 8
8 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
9 REFSEL 38.4 Clock Gen Fractional 1 1 130.2083333 130 781250 3750000 Third Enabled 5000 4
10 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
11 REFSEL 77.76 Clock Gen Integer 1 1 64 64 0 1 n/a Disabled 4976.64 8
12 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
13 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
14 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
15 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
16 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
17 REFSEL 77.76 Disabled 1 1 1 1 0 1 n/a n/a n/a 8
18 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
19 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
20 REFSEL 50 Disabled 1 1 1 1 0 1 n/a n/a n/a 8
21 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
22 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
23 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
24 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
25 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
26 REFSEL 50 Disabled 1 1 1 1 0 1 n/a n/a n/a 8
27 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
28 REFSEL 50 Disabled 1 1 1 1 0 1 n/a n/a n/a 8
29 REFSEL 50 Disabled 1 1 1 1 0 1 n/a n/a n/a 8
30 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
31 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
32 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
33 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
34 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
35 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
36 REFSEL 77.76 Clock Gen Fractional 1 1 61.728395 61 2913580 4000000 Third Enabled 4800 6
37 REFSEL 38.4 Clock Gen Integer 1 1 125 125 0 1 n/a Disabled 4800 6
38 REFSEL 50 Disabled 1 1 1 1 0 1 n/a n/a n/a 8
39 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 4
40 REFSEL 81.92 Clock Gen Fractional 1 1 58.59375 58 2375000 4000000 Third Enabled 4800 4
41 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
42 REFSEL 81.92 Clock Gen Fractional 1 1 58.59375 58 2375000 4000000 Third Enabled 4800 6
43 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
44 REFSEL 81.92 Clock Gen Fractional 1 1 58.59375 58 2375000 4000000 Third Enabled 4800 6
45 REFSEL 54 Clock Gen Integer 1 1 99 99 0 1 n/a Disabled 5346 6
46 REFSEL 54 Clock Gen Integer 1 1 99 99 0 1 n/a Disabled 5346 6
47 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
48 REFSEL 77.76 Clock Gen Integer 1 1 64 64 0 1 n/a Disabled 4976.64 8
49 REFSEL 50 Clock Gen Fractional 1 1 99.5328 99 2131200 4000000 Third Enabled 4976.64 8
50 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
51 PRI 112 Clock Gen Fractional 1 1 45.98214286 45 3604480 3670016 Third Enabled 5150 5
52 PRI 112 Clock Gen Fractional 1 1 44.14285714 44 524288 3670016 Third Enabled 4944 4
53 REFSEL 50 Clock Gen Fractional 1 1 98.304 98 1216000 4000000 Third Enabled 4915.2 8
54 REFSEL 77.76 Clock Gen Integer 1 1 64 64 0 1 n/a Disabled 4976.64 8
55 REFSEL 77.76 Disabled 1 1 1 1 0 1 n/a n/a n/a 8
56 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
57 REFSEL 50 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
58 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
59 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
60 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
61 REFSEL 50 Disabled 1 1 1 1 0 1 n/a n/a n/a 8
62 REFSEL 50 Clock Gen Integer 1 1 96 96 0 1 n/a Disabled 4800 6
63 REFSEL 77.76 Clock Gen Fractional 1 1 68.8607595 68 1721519 2000000 Third Enabled 5354.6127 8
(1) When PLL2 is set as an integer-based clock generator, external loop filter component, C2, should be 3.3nF and loop bandwidth is around 400kHz. When PLL2 is set as a fractional-based clock generator, external loop filter component, C2, should be 33nF and loop bandwidth is around 400kHz.
(2) Refer to Table 3 when entry is REFSEL.

Table 18. Default ROM Contents (HW_SW_CTRL = "1") - Outputs [0-3] Configuration

GPIO[5:0] (decimal) OUT0-1 DIVIDER OUT0-1 FREQ (MHz) OUT0-1 MUX SELECT OUT0 TYPE OUT1 TYPE OUT2-3 DIVIDER OUT2-3 FREQ (MHz) OUT2-3 MUX SELECT OUT2 TYPE OUT3 TYPE
0 25 25 PLL1 LVCMOS LVCMOS 25 25 PLL1 LVCMOS LVCMOS
1 4 156.25 PLL1 LVPECL LVPECL 25 25 PLL1 LVPECL LVPECL
2 4 156.25 PLL1 CML CML 4 156.25 PLL1 LVPECL LVPECL
3 10 100 PLL1 LVPECL LVPECL 10 100 PLL1 LVPECL LVPECL
4 16 156.25 PLL1 LVPECL LVPECL 25 100 PLL2 HCSL HCSL
5 16 156.25 PLL1 LVPECL CML 25 100 PLL2 LVPECL CML
6 16 156.25 PLL1 LVPECL CML 25 100 PLL2 LVPECL CML
7 25 100 PLL1 LVPECL LVPECL 25 100 PLL1 CML CML
8 16 156.25 PLL1 LVPECL Disable 25 100 PLL2 LVPECL LVPECL
9 5 122.88 PLL1 LVPECL LVPECL 5 122.88 PLL1 LVDS LVDS
10 4 156.25 PLL2 LVPECL Disable 6 100 PLL1 CML CML
11 16 155.52 PLL2 HCSL HCSL 16 38.88 PLL2 HCSL Disable
12 20 125 PLL1 LVPECL LVPECL 100 25 PLL2 LVPECL LVPECL
13 16 156.25 PLL1 LVDS LVDS 20 125 PLL1 LVDS LVDS
14 16 156.25 PLL1 LVPECL LVPECL 25 100 PLL2 LVPECL CML
15 20 125 PLL1 LVPECL LVPECL 100 25 PLL2 LVPECL LVPECL
16 4 156.25 PLL2 LVPECL CML 5 125 PLL2 CML CML
17 1 622.08 PLL1 LVPECL Disable 4 155.52 PLL1 LVPECL LVPECL
18 25 100 PLL2 CML CML 20 125 PLL1 CML CML
19 4 156.25 PLL2 LVPECL LVPECL 5 125 PLL2 LVPECL LVPECL
20 12 100 PLL1 LVPECL LVPECL 12 100 PLL1 LVPECL LVPECL
21 16 156.25 PLL1 LVDS LVDS 25 100 PLL2 LVDS LVDS
22 16 156.25 PLL1 LVPECL LVPECL 20 125 PLL1 LVPECL LVPECL
23 4 156.25 PLL2 LVDS LVDS 12 100 PLL1 HCSL HCSL
24 20 125 PLL1 LVDS LVDS 25 100 PLL2 LVDS LVDS
25 4 156.25 PLL2 LVPECL LVPECL 12 100 PLL1 LVPECL LVPECL
26 12 100 PLL1 LVDS LVDS 12 100 PLL1 LVDS LVDS
27 16 156.25 PLL1 LVPECL LVPECL 25 100 PLL2 LVPECL LVPECL
28 16 156.25 PLL1 LVPECL LVPECL 16 156.25 PLL1 LVPECL LVPECL
29 16 156.25 PLL1 LVPECL LVPECL 16 156.25 PLL1 LVPECL LVPECL
30 4 156.25 PLL2 LVPECL LVPECL 5 125 PLL2 LVPECL LVPECL
31 16 156.25 PLL1 LVPECL CML 25 100 PLL2 LVPECL CML
32 16 156.25 PLL1 LVPECL CML 20 125 PLL1 LVPECL CML
33 5 125 PLL2 LVPECL LVPECL 24 25 PLL1 LVPECL LVPECL
34 20 125 PLL1 LVPECL LVPECL 25 100 PLL2 LVPECL LVPECL
35 16 156.25 PLL1 LVPECL LVPECL 25 100 PLL2 LVPECL LVPECL
36 16 156.25 PLL1 LVPECL LVPECL 25 100 PLL2 LVPECL LVPECL
37 16 156.25 PLL1 LVPECL LVPECL 25 100 PLL2 LVPECL LVPECL
38 100 25 PLL1 LVCMOS LVCMOS 100 25 PLL1 LVCMOS LVCMOS
39 24 50 PLL1 LVDS LVDS 12 100 PLL1 LVPECL LVPECL
40 24 50 PLL2 LVDS LVDS 12 100 PLL2 LVPECL LVPECL
41 50 50 PLL2 LVDS LVDS 25 100 PLL2 LVPECL LVPECL
42 50 50 PLL2 LVDS LVDS 25 100 PLL2 LVPECL LVPECL
43 16 156.25 PLL1 LVPECL LVPECL 25 100 PLL2 LVPECL LVPECL
44 16 156.25 PLL1 LVPECL LVPECL 25 100 PLL2 LVPECL LVPECL
45 25 100 PLL1 LVPECL LVPECL 6 148.5 PLL2 CML CML
46 6 148.5 PLL2 LVPECL LVPECL 1 n/a n/a Disable Disable
47 16 156.25 PLL1 LVPECL LVPECL 16 156.25 PLL1 LVPECL LVPECL
48 4 155.52 PLL2 LVPECL Disable 8 77.76 PLL2 LVCMOS LVCMOS
49 4 155.52 PLL2 LVPECL LVPECL 20 125 PLL1 LVPECL LVPECL
50 16 156.25 PLL1 LVPECL LVPECL 20 125 PLL1 LVPECL LVPECL
51 2 515 PLL2 LVPECL LVPECL 5 125 PLL1 LVPECL Disable
52 5 125 PLL1 LVPECL Disable 3 412 PLL2 LVPECL Disable
53 40 25 PLL1 LVCMOS Disable 1 n/a n/a Disable Disable
54 4 155.52 PLL2 LVPECL LVPECL 16 156.25 PLL1 LVPECL LVPECL
55 25 25 PLL1 LVCMOS LVCMOS 25 25 PLL1 LVCMOS LVCMOS
56 4 156.25 PLL2 LVPECL LVPECL 12 100 PLL1 LVPECL LVPECL
57 4 156.25 PLL2 CML CML 4 156.25 PLL2 CML CML
58 16 156.25 PLL1 LVPECL LVPECL 16 156.25 PLL1 LVPECL LVPECL
59 16 156.25 PLL1 LVPECL LVPECL 16 156.25 PLL1 LVPECL LVPECL
60 16 156.25 PLL1 LVPECL LVPECL 16 156.25 PLL1 LVPECL LVPECL
61 16 156.25 PLL1 LVPECL LVPECL 16 156.25 PLL1 LVPECL LVPECL
62 16 156.25 PLL1 LVPECL LVPECL 25 100 PLL2 LVPECL LVPECL
63 4 167.3316456 PLL2 LVPECL LVPECL 4 167.3316456 PLL2 LVPECL LVPECL

Table 19. Default ROM Contents (HW_SW_CTRL = "1") - Outputs [4-7] Configuration

GPIO
[5:0]
(decimal)		 OUT4 DIV OUT4 FREQ (MHz) OUT4 MUX SEL OUT4 TYPE OUT5 DIV OUT5 FREQ (MHz) OUT5 MUX SEL OUT5 TYPE OUT6 DIV OUT6 FREQ (MHz) OUT6 MUX SEL OUT6 TYPE OUT7 DIV OUT7 FREQ (MHz) OUT7 MUX SEL OUT7 TYPE
0 25 25 PLL1 LVCMOS 25 25 PLL1 LVCMOS 25 25 PLL1 LVCMOS 25 25 PLL1 LVCMOS
1 4 156.25 PLL1 LVDS 1 n/a n/a Disable 5 125 PLL1 LVCMOS 5 125 PLL1 LVCMOS
2 5 125 PLL1 LVCMOS 5 125 PLL1 LVCMOS 5 125 PLL1 LVCMOS 25 25 PLL1 LVCMOS
3 8 125 PLL1 LVCMOS 8 125 PLL1 LVCMOS 8 125 PLL1 LVCMOS 40 25 PLL1 LVCMOS
4 25 100 PLL2 HCSL 25 100 PLL2 HCSL 100 25 PLL2 LVPECL 100 25 PLL2 LVPECL
5 25 100 PLL2 HCSL 25 100 PLL2 LVCMOS 20 125 PLL1 LVCMOS 50 50 PLL2 LVCMOS
6 25 100 PLL2 HCSL 20 125 PLL1 HCSL 20 125 PLL1 LVCMOS 25 100 PLL2 LVCMOS
7 25 100 PLL1 LVCMOS 20 125 PLL1 LVCMOS 100 25 PLL1 LVCMOS 100 25 PLL1 LVCMOS
8 25 100 PLL2 HCSL 25 100 PLL2 HCSL 1 n/a n/a Disable 100 25 PLL2 LVCMOS
9 5 122.88 PLL1 LVDS 8 156.25 PLL2 LVDS 10 125 PLL2 LVDS 125 10 PLL2 LVCMOS
10 5 125 PLL2 LVDS 6 100 PLL1 HCSL 6 100 PLL1 LVCMOS 25 24 PLL1 LVCMOS
11 16 156.25 PLL1 HCSL 20 125 PLL1 HCSL 25 100 PLL1 HCSL 100 25 PLL1 LVCMOS
12 16 156.25 PLL1 LVDS 1 n/a n/a Disable 25 100 PLL2 HCSL 25 100 PLL2 LVCMOS
13 1 n/a n/a Disable 25 100 PLL2 HCSL 1 n/a n/a Disable 100 25 PLL2 LVCMOS
14 1 n/a n/a Disable 100 25 PLL2 LVDS 100 25 PLL2 LVCMOS 25 100 PLL2 LVCMOS
15 25 100 PLL2 HCSL 1 n/a n/a Disable 25 100 PLL2 LVCMOS 100 25 PLL2 LVCMOS
16 6 100 PLL1 HCSL 12 50 PLL1 LVCMOS 24 25 PLL1 LVCMOS 50 12 PLL1 LVCMOS
17 4 155.52 PLL1 LVDS 4 155.52 PLL1 LVDS 8 77.76 PLL1 LVDS 8 77.76 PLL1 LVDS
18 20 125 PLL1 LVCMOS 25 100 PLL2 LVCMOS 100 25 PLL2 LVCMOS 30 83.3333 PLL1 LVCMOS
19 48 25 PLL1 LVPECL 12 100 PLL1 LVPECL 1 n/a n/a Disable 18 66.6666 PLL1 LVCMOS
20 1 n/a n/a Disable 48 25 PLL1 LVCMOS 1 n/a n/a Disable 18 66.6666 PLL1 LVCMOS
21 25 100 PLL2 LVDS 1 n/a n/a Disable 1 n/a n/a Disable 100 25 PLL2 LVCMOS
22 25 100 PLL2 LVPECL 1 n/a n/a Disable 1 n/a n/a Disable 100 25 PLL2 LVCMOS
23 48 25 PLL1 LVDS 48 25 PLL1 LVDS 18 66.6666 PLL1 LVCMOS 9 133.3333 PLL1 LVDS
24 25 100 PLL2 LVDS 25 100 PLL2 LVCMOS 100 25 PLL2 LVDS 100 25 PLL2 LVCMOS
25 12 100 PLL1 HCSL 1 n/a n/a Disable 18 66.6666 PLL1 LVCMOS 48 25 PLL1 LVCMOS
26 9 133.3333 PLL1 LVDS 48 25 PLL1 LVDS 48 25 PLL1 LVCMOS 18 66.6666 PLL1 LVCMOS
27 50 50 PLL2 LVPECL 20 125 PLL1 LVPECL 25 100 PLL2 LVCMOS 100 25 PLL2 LVCMOS
28 16 156.25 PLL1 LVPECL 16 156.25 PLL1 LVPECL 16 156.25 PLL1 LVPECL 100 25 PLL1 LVCMOS
29 100 25 PLL1 LVCMOS 100 25 PLL1 LVCMOS 16 156.25 PLL1 LVPECL 100 25 PLL1 LVCMOS
30 9 133.33 PLL1 LVDS 12 100 PLL1 HCSL 12 100 PLL1 HCSL 48 25 PLL1 LVCMOS
31 25 100 PLL2 HCSL 25 100 PLL2 HCSL 100 25 PLL2 LVDS 100 25 PLL2 HCSL
32 25 100 PLL2 HCSL 100 25 PLL2 LVDS 50 50 PLL2 LVCMOS 75 33.3333 PLL2 LVCMOS
33 4 156.25 PLL2 LVDS 1 n/a n/a Disable 6 100 PLL1 LVDS 50 12 PLL1 LVCMOS
34 16 156.25 PLL1 LVDS 1 n/a n/a Disable 100 25 PLL2 LVCMOS 100 25 PLL2 LVCMOS
35 1 n/a n/a Disable 1 n/a n/a Disable 100 25 PLL2 LVCMOS 100 25 PLL2 LVCMOS
36 1 n/a n/a Disable 1 n/a n/a Disable 100 25 PLL2 LVCMOS 100 25 PLL2 LVCMOS
37 1 n/a n/a Disable 1 n/a n/a Disable 100 25 PLL2 LVCMOS 100 25 PLL2 LVCMOS
38 100 25 PLL1 LVCMOS 100 25 PLL1 LVCMOS 100 25 PLL1 LVCMOS 100 25 PLL1 LVCMOS
39 8 156.25 PLL2 LVPECL 10 125 PLL2 LVPECL 9 133.3333 PLL1 LVDS 50 24 PLL1 LVCMOS
40 8 156.25 PLL1 LVPECL 10 125 PLL1 LVPECL 9 133.3333 PLL2 LVDS 50 24 PLL2 LVCMOS
41 16 156.25 PLL1 LVPECL 8 312.5 PLL1 LVPECL 20 125 PLL1 LVPECL 25 100 PLL2 LVCMOS
42 16 156.25 PLL1 LVPECL 8 312.5 PLL1 LVPECL 20 125 PLL1 LVPECL 25 100 PLL2 LVCMOS
43 8 312.5 PLL1 LVPECL 25 100 PLL2 LVCMOS 50 50 PLL2 LVCMOS 100 25 PLL2 LVCMOS
44 8 312.5 PLL1 LVPECL 25 100 PLL2 LVCMOS 50 50 PLL2 LVCMOS 100 25 PLL2 LVCMOS
45 25 100 PLL1 LVPECL 33 27 PLL2 LVCMOS 100 25 PLL1 LVCMOS 100 25 PLL1 LVCMOS
46 16 38.88 PLL1 LVCMOS 16 38.88 PLL1 LVCMOS 12 74.25 PLL2 LVCMOS 33 27 PLL2 LVCMOS
47 20 125 PLL1 HCSL 25 100 PLL2 HCSL 1 n/a n/a Disable 100 25 PLL2 LVCMOS
48 20 125 PLL1 LVPECL 16 156.25 PLL1 LVPECL 25 100 PLL1 LVPECL 8 77.76 PLL2 LVDS
49 25 100 PLL1 LVPECL 25 100 PLL1 LVPECL 16 156.25 PLL1 LVPECL 100 25 PLL1 LVCMOS
50 25 100 PLL2 LVPECL 25 100 PLL2 LVPECL 25 100 PLL2 LVPECL 100 25 PLL2 LVCMOS
51 1 n/a n/a Disable 25 25 PLL1 LVCMOS 1 n/a n/a Disable 10 103 PLL2 LVCMOS
52 4 309 PLL2 LVPECL 1 n/a n/a Disable 25 25 PLL1 LVCMOS 12 103 PLL2 LVCMOS
53 15 66.6666 PLL1 LVCMOS 1 n/a n/a Disable 1 n/a n/a Disable 15 40.96 PLL2 LVCMOS
54 16 156.25 PLL1 LVPECL 20 125 PLL1 LVPECL 25 100 PLL1 LVPECL 100 25 PLL1 LVCMOS
55 25 25 PLL1 LVCMOS 25 25 PLL1 LVCMOS 25 25 PLL1 LVCMOS 25 25 PLL1 LVCMOS
56 12 100 PLL1 LVPECL 48 25 PLL1 LVPECL 1 n/a n/a Disable 18 66.6666 PLL1 LVCMOS
57 12 100 PLL1 CML 48 25 PLL1 LVPECL 24 50 PLL1 LVPECL 18 66.6666 PLL1 LVCMOS
58 25 100 PLL2 LVPECL 100 25 PLL2 LVPECL 100 25 PLL2 LVPECL 25 100 PLL2 LVCMOS
59 25 100 PLL2 LVPECL 100 25 PLL2 LVPECL 100 25 PLL2 LVCMOS 25 100 PLL2 LVCMOS
60 25 100 PLL2 LVPECL 100 25 PLL2 LVPECL 100 25 PLL2 LVPECL 25 100 PLL2 LVPECL
61 16 156.25 PLL1 LVPECL 16 156.25 PLL1 LVPECL 16 156.25 PLL1 LVPECL 16 156.25 PLL1 LVPECL
62 16 156.25 PLL1 LVPECL 100 25 PLL2 LVPECL 100 25 PLL2 LVCMOS 25 100 PLL2 LVCMOS
63 16 156.25 PLL1 LVPECL 16 156.25 PLL1 LVPECL 20 125 PLL1 LVDS 25 100 PLL1 HCSL