SNAS668D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
The INT_FLAG register records rising or falling edges on the interrupt sources. The polarity is controlled by the INT_FLAG_POL register. This register is only updated if the INT_EN register bit is set to 1.
Bit # | Field | Type | Reset | EEPROM | Description |
---|---|---|---|---|---|
[7] | LOL1_INTR | R | 0 | N | LOL1 Interrupt. The LOL1_INTR bit is set when an edge of the correct polarity is detected on the LOL1 interrupt source. The LOL1_INTR bit is cleared by writing a 0. |
[6] | LOS1_INTR | R | 0 | N | LOS1 Interrupt. The LOS1_INTR bit is set when an edge of the correct polarity is detected on the LOS1 interrupt source. The LOS1_INTR bit is cleared by writing a 0. |
[5] | CAL1_INTR | R | 0 | N | CAL1 Interrupt. The CAL1_INTR bit is set when an edge of the correct polarity is detected on the CAL1 interrupt source. The CAL1_INTR bit is cleared by writing a 0. |
[4] | LOL2_INTR | R | 0 | N | LOL2 Interrupt. The LOL2_INTR bit is set when an edge of the correct polarity is detected on the LOL2 interrupt source. The LOL2_INTR bit is cleared by writing a 0. |
[3] | LOS2_INTR | R | 0 | N | LOS2 Interrupt. The LOS2_INTR bit is set when an edge of the correct polarity is detected on the LOS2 interrupt source. The LOS2_INTR bit is cleared by writing a 0. |
[2] | CAL2_INTR | R | 0 | N | CAL2 Interrupt. The CAL2_INTR bit is set when an edge of the correct polarity is detected on the CAL2 interrupt source. The CAL2_INTR bit is cleared by writing a 0. |
[1] | SECTOPRI1_INTR | R | 0 | N | SECTOPRI1 Interrupt. The SECT2PRI1_INTR bit is set when an edge of the correct polarity is detected on the SECTOPRI1 interrupt source. The SECTOPRI1_INTR bit is cleared by writing a 0. |
[0] | SECTOPRI2_INTR | R | 0 | N | SECTOPRI2 Interrupt. The SECTOPRI2_INTR bit is set when an edge of the correct polarity is detected on the SECTOPRI2 interrupt source. The SECTOPRI2_INTR bit is cleared by writing a 0. |