4 Revision History
Changes from C Revision (December 2017) to D Revision
- Clarified note about VOH (rail-to-rail swing only with VDDO = 1.8 V +/- 5%)Go
- Changed Slew Rate minimum and maximum from: 2.25 V/ns and 5 V/ns to: 1 V/ns and 4 V/ns, respectively Go
- Updated REVID to be 0x02 (was 0x01) Go
- Added the Support for PCB Temperature up to 105°C subsectionGo
Changes from B Revision (August 2016) to C Revision
- Added bullets to the Applications section Go
- Added a table note to Recommended Operating Conditions explaining the NOM values.Go
- Added PCIe Clock Output Jitter tableGo
- Changed Figure 45 text from: Vbb = 1.3 V to: Vbb = 1.8 VGo
- Added tablenotes to Table 10Go
- Updated PLL2_CTRL1 Register; R72's Icp values to match those found in PLL1_CTRL1 Register; R57 .Go
- Changed the first paragraph of the Powering Up From Single Supply Rail section Go
- Changed the first paragraph of the Powering Up From Split Supply Rails section and Figure 86Go
- Changed the first paragraph and added new content to the Slow Power-Up Supply Ramp section Go
- Changed the first paragraph of the Non-Monotonic Power-Up Supply Ramp section Go
Changes from A Revision (January 2016) to B Revision
- Modified default ROM contents on Input and Status configurations Go
- Modified default ROM contents on PLL1 configurations Go
- Modified default ROM contents on PLL2 configurations Go