SNAS663B March   2017  – July 2019 LMK04616

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Simplified Schematic
  4. 4Revision History
  5. 5Device and Documentation Support
    1. 5.1 Device Support
      1. 5.1.1 Development Support
        1. 5.1.1.1 Clock Design Tool
        2. 5.1.1.2 Clock Architect
        3. 5.1.1.3 TICS Pro
    2. 5.2 Receiving Notification of Documentation Updates
    3. 5.3 Community Resources
    4. 5.4 Trademarks
    5. 5.5 Electrostatic Discharge Caution
    6. 5.6 Glossary
  6. 6Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from A Revision (May 2017) to B Revision

  • Removed bulleted list under the Dual Loop PLL Architecture feature bulletGo
  • Added Ultra Low Noise feature bulletsGo
  • Changed VCO frequency units from: 5.8 to 6.175 GHz to: 5870 MHz to 6175 MHzGo

Changes from * Revision (March 2017) to A Revision

  • Changed text from: –70-dBc PSRR to: –80dBc PSRR on VDDOGo
  • Changed SPI Interface default from: 3-wire to: 4-wire Go
  • Changed VCO frequency from: 5.8 to 6.2 GHz to: 5.8 to 6.175 GHzGo