SNVSAC1 June   2015 LMR16006Y-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fixed Frequency PWM Control
      2. 8.3.2 Bootstrap Voltage (CB)
      3. 8.3.3 Output Voltage Setting
      4. 8.3.4 Enable SHDN and VIN Undervoltage Lockout
      5. 8.3.5 Current Limit
      6. 8.3.6 Overvoltage Transient Protection
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conduction Mode
      2. 8.4.2 ECO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Schottky Diode Selection
        4. 9.2.2.4 Input Capacitor Selection
        5. 9.2.2.5 Bootstrap Capacitor Selection
      3. 9.2.3 Application Curves
      4. 9.2.4 Additional Application Circuit
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

DDC Package
6-Pin SOT
Top View
LMR16006Y-Q1 pin_config_snvsac1.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NUMBER
CB 1 I Switch FET gate bias voltage. Connect Cboot capacitor between CB and SW.
GND 2 G Ground connection.
FB 3 I Feedback Input. Set feedback voltage divider ratio with VOUT = VFB (1 + (R1/R2)).
SHDN 4 I Enable and disable input (high voltage tolerant). Internal pull-up current source. Pull below 1.25 V to disable. Float to enable. Establish input undervoltage lockout with two resistor divider.
VIN 5 I Power input voltage pin. Input for internal supply and drain node input for internal high-side MOSFET.
SW 6 O Switch node. Connect to inductor, diode, and Cboot capacitor.