SNAS646F December   2015  – November 2017 LMX2592

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Functional Description
      1. 7.3.1  Input Signal
      2. 7.3.2  Input Signal Path
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
      5. 7.3.5  Voltage Controlled Oscillator
      6. 7.3.6  VCO Calibration
      7. 7.3.7  VCO Doubler
      8. 7.3.8  Channel Divider
      9. 7.3.9  Output Distribution
      10. 7.3.10 Output Buffer
      11. 7.3.11 Phase Adjust
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Lock Detect
      3. 7.4.3 Register Readback
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1 LMX2592 Register Map - Default Values
        1. 7.6.1.1 Register Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Optimization of Spurs
        1. 8.1.1.1 Understanding Spurs by Offsets
        2. 8.1.1.2 Spur Mitigation Techniques
      2. 8.1.2 Configuring the Input Signal Path
        1. 8.1.2.1 Input Signal Noise Scaling
      3. 8.1.3 Input Pin Configuration
      4. 8.1.4 Using the OSCin Doubler
      5. 8.1.5 Using the Input Signal Path Components
        1. 8.1.5.1 Moving Phase Detector Frequency
        2. 8.1.5.2 Multiplying and Dividing by the Same Value
      6. 8.1.6 Designing for Output Power
      7. 8.1.7 Current Consumption Management
      8. 8.1.8 Decreasing Lock Time
      9. 8.1.9 Modeling and Understanding PLL FOM and Flicker Noise
    2. 8.2 Typical Application
      1. 8.2.1 Design for Low Jitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHA|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Output Frequency Range from 20 to 9800 MHz
  • Industry Leading Phase Noise Performance
    • VCO Phase Noise: –134.5 dBc/Hz at 1-MHz Offset for 6-GHz Output
    • Normalized PLL Noise Floor: –231 dBc/Hz
    • Normalized PLL Flicker Noise: –126 dBc/Hz
    • 49-fs RMS Jitter (12 kHz to 20 MHz) for 6 GHz Output
  • Input Clock Frequency Up to 1400 MHz
  • Phase Detector Frequency Up to 200 MHz,
    and Up to 400 MHz in Integer-N Mode
  • Supports Fractional-N and Integer-N Modes
  • Dual Differential Outputs
  • Innovative Solution to Reduce Spurs
  • Programmable Phase Adjustment
  • Programmable Charge Pump Current
  • Programmable Output Power Level
  • SPI or uWire (4-Wire Serial Interface)
  • Single Power Supply Operation: 3.3 V

Applications

  • Test and Measurement Equipment
  • Defense and RADAR
  • Microwave Backhaul
  • High-Performance Clock Source for High-Speed Data Converters
  • Satellite Communications

Description

The LMX2592 device is a low-noise, wideband RF PLL with integrated VCO that supports a frequency range from 20 MHz to 9.8 GHz. The device supports both fractional-N and integer-N modes, with a 32-bit fractional divider allowing fine frequency selection. Integrated noise of 49 fs for 6-GHz output makes it an ideal low-noise source. Combining best-in-class PLL and integrated VCO noise with integrated LDOs, this device removes the need for multiple discrete devices in high performance systems.

The device accepts input frequencies up to 1.4 GHz, which combined with frequency dividers and programmable low noise multiplier allows flexible frequency planning. The additional programmable low-noise multiplier lets users mitigate the impact of integer boundary spurs. In Fractional-N mode, the device can adjust the output phase by a 32-bit resolution. For applications that need fast frequency changes, the device supports a fast calibration option which takes less than 25 µs.

This performance is achieved by using single 3.3-V supply. It supports 2 flexible differential outputs that can be configured as single-ended outputs as well. Users can choose to program one output from the VCO (or doubler) and the second from the channel divider. When not being used, each output can be muted separately.

Device Information (1)

PART NUMBER DESCRIPTION BODY SIZE (NOM)
LMX2592RHAT
LMX2592RHAR
WQFN (40) 6.00 mm × 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.
  2. T = Tape; R = Reel

Simplified Schematic

LMX2592 LMX2592_block_diagram_snas680.gif