SNAS646F December   2015  – November 2017 LMX2592

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Functional Description
      1. 7.3.1  Input Signal
      2. 7.3.2  Input Signal Path
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
      5. 7.3.5  Voltage Controlled Oscillator
      6. 7.3.6  VCO Calibration
      7. 7.3.7  VCO Doubler
      8. 7.3.8  Channel Divider
      9. 7.3.9  Output Distribution
      10. 7.3.10 Output Buffer
      11. 7.3.11 Phase Adjust
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Lock Detect
      3. 7.4.3 Register Readback
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1 LMX2592 Register Map - Default Values
        1. 7.6.1.1 Register Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Optimization of Spurs
        1. 8.1.1.1 Understanding Spurs by Offsets
        2. 8.1.1.2 Spur Mitigation Techniques
      2. 8.1.2 Configuring the Input Signal Path
        1. 8.1.2.1 Input Signal Noise Scaling
      3. 8.1.3 Input Pin Configuration
      4. 8.1.4 Using the OSCin Doubler
      5. 8.1.5 Using the Input Signal Path Components
        1. 8.1.5.1 Moving Phase Detector Frequency
        2. 8.1.5.2 Multiplying and Dividing by the Same Value
      6. 8.1.6 Designing for Output Power
      7. 8.1.7 Current Consumption Management
      8. 8.1.8 Decreasing Lock Time
      9. 8.1.9 Modeling and Understanding PLL FOM and Flicker Noise
    2. 8.2 Typical Application
      1. 8.2.1 Design for Low Jitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHA|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

Optimization of Spurs

Understanding Spurs by Offsets

The first step in optimizing spurs is to be able to identify them by offset. Figure 23 gives a good example that can be used to isolate the following spur types.

LMX2592 SpurFrequencies.gif Figure 23. Spur Offset Frequency Example

Based on Figure 23, the most common spurs can be calculated from the frequencies. Note that the % is the modulus operator and is meant to mean the difference to the closest integer multiple. Some examples of how to use this operator are: 36 % 11 = 3, 1000.1 % 50 = 0.1, and 5023.7 % 122.88 = 14.38. Applying this concept, the spurs at various offsets can be identified from Figure 23.

Table 48. Spur Definition Table

SPUR TYPE OFFSET OFFSET IN Figure 23 COMMENTS
OSCin fOSC 40 MHz This spur occurs at harmonics of the OSCin frequency.
Fpd fPD 120 MHz The phase detector spur has many possible mechanisms and occurs at multiples of the phase detector frequency.
fOUT % fOSC fOUT % fOSC 606.25 % 40 = 6.25 MHz This spur is caused by mixing between the output and input frequencies.
fVCO% fOSC fVCO % fOSC 4850 % 40 = 10 MHz This spur is caused by mixing between the VCO and input frequencies.
fVCO% fPD fVCO % fPD 4850 % 120 = 50 MHz This spur would be the same offset as the integer boundary spur if PLL_N_PRE=1, but can be different if this value is greater than one.
Integer Boundary fPD *(Fnum%Fden)/ Fden) 120 × (5%24)/24 = 25 MHz This is a single spur
Primary Fractional fPD / Fden 120 / 24 = 5 MHz The primary fractional
Sub-Fractional fPD / Fden / k

k=2,3, or 6
First Order Modulator: None
2nd Order Modulator: 120/24/2 = 2.5 MHz
3rd Order Modulator: 120/24/6 = 0.83333 MHz
4th Order Modulator: 120/24/12 = 0.416666 MHz
To Calculate k:
1st Order Modulator: k=1
2nd Order Modulator: k=1 if Fden is odd, k=2 if Fden is even
3rd Order Modulator: k=1 if Fden not divisible by 2 or 3, k=2 if Fden divisible by 2 not 3, k=3 if Fden divisible by 3 but not 2, Fden = 6 if Fden divisible by 2 and 3
4th Order Modulator: k=1 if Fden not divisible by 2 or 3. k=3 if Fden divisible by 3 but not 2, k=4 if Fden divisible by 2 but not 3, k=12 if Fden divisible by 2 and 3
Sub-Fractional Spurs exist if k>1

In the case that two different spur types occur at the same offset, either name would be correct. Some may name this by the more dominant cause, while others would simply name by choosing the name that is near the top of Table 48.

Spur Mitigation Techniques

Once the spur is identified and understood, there will likely be a desire to try to minimize them. Table 49 gives some common methods.

Table 49. Spurs and Mitigation Techniques

SPUR TYPE WAYS TO REDUCE TRADE-OFF
OSCin
  1. Use PLL_N_PRE = 2
  2. Use an OSCin signal with low amplitude and high slew rate (like LVDS).
Phase Detector
  1. Decrease PFD_DLY
  2. To pin 11, use a series ferrite bead and a shunt 0.1-µF capacitor.
fOUT % fOSC Use an OSCin signal with low amplitude and high slew rate (like LVDS)
fVCO% fOSC
  1. To pin 7, use a series ferrite bead and a shunt 0.1-µF capacitor.
  2. Increase the offset of this spur by shifting the VCO frequency
  3. If multiple VCO frequencies are posslble that yield the same spur offset, choose the higher VCO frequency.
.
fVCO% fPD Avoid this spur by shifting the phase detector frequency (with the programmable input multiplier or R divider) or shifting the VCO frequency. This spur is better at higher VCO frequency.
Integer Boundary

Methods for PLL Dominated Spurs

  1. Avoid the worst case VCO frequencies if possible.
  2. Strategically choose which VCO core to use if possible.
  3. Ensure good slew rate and signal integrity at the OSCin pin
  4. Reduce the loop bandwidth or add more filter poles for out of band spurs
  5. Experiment with modulator order and PFD_DLY
Reducing the loop bandwidth may degrade the total integrated noise if the bandwidth is too narrow.

Methods for VCO Dominated Spurs

  1. Avoid the worst case VCO frequencies if possible.
  2. Reduce Phase Detector Frequency
  3. Ensure good slew rate and signal integrity at the OSCin pin
  4. Make the impedance looking outwards from the OSCin pin close to 50 Ω.
Reducing the phase detector may degrade the phase noise and also reduce the capacitance at the Vtune pin.
Primary Fractional
  1. Decrease Loop Bandwidth
  2. Change Modulator Order
  3. Use Larger Unequivalent Fractions
Decreasing the loop bandwidth too much may degrade in-band phase noise. Also, larger unequivalent fractions only sometimes work
Sub-Fractional
  1. Use Dithering
  2. Use MASH seed
  3. Use Larger Equivalent Fractions
  4. Use Larger Unequivalent Fractions
  5. Reduce Modulator Order
  6. Eliminate factors of 2 or 3 in denominator (see AN-1879 Fractional N Frequency Synthesis (SNAA062)
Dithering and larger fractions may increase phase noise. MASH_SEED can be set between values 0 and Fden, which changes the sub-fractional spur behavior. This is a deterministic relationship and there will be one seed value that will give best result for this spur.

Configuring the Input Signal Path

The input path is considered the portion of the device between the OSCin pin and the phase detector, which includes the input buffer, R dividers, and programmable multipliers. The way that these are configured can have a large impact on phase noise and fractional spurs.

Input Signal Noise Scaling

The input signal noise scales by 20 × log(output frequency / input signal frequency), so always check this to see if the noise of the input signal scaled to the output frequency is close to the PLL in-band noise level. When that happens, the input signal noise is the dominant noise source, not the PLL noise floor.

LMX2592 older_D001_input_scaling_low_noise_SNAS680.gif
Figure 24. Phase Noise of 5.4-GHz Output
With Low-Noise Input Signal
LMX2592 older_D002_input_scaling_high_noise_SNAS680.gif
Figure 25. Phase Noise of 5.4-GHz Output
With High-Noise Input Signal

Input Pin Configuration

The OSCinM and OSCinP can be used to support both a single-ended or differential clock. In either configuration, the termination on both sides should match for best common-mode noise rejection. The slew rate and signal integrity of this signal can have an impact on both the phase noise and fractional spurs. Standard clocking types, LVDS, LVPECL, HCSL, and CMOS can all be used.

Using the OSCin Doubler

The lowest PLL flat noise is achieved with a low-noise 200-MHz input signal. If only a low-noise input signal with lower frequency is available (for example a 100-MHz source), you can use the low noise OSCin doubler to attain 200-MHz phase detector frequency. Because PLL_flat = PLL_FOM + 20 × log(Fvco/Fpd) + 10 × log(Fpd / 1Hz), doubling Fpd theoretically gets –6 dB from the 20 × log(Fvco/Fpd) component, +3 dB from the 10 × log(Fpd / 1Hz) component, and cumulatively a –3-dB improvement.

LMX2592 older_D008_osc2x_SNAS680.gif Figure 26. 100MHz Input With OSCin Doubler

Using the Input Signal Path Components

The ideal input is a low-noise, 200-MHz (or multiples of it) signal and 200-MHz phase detector frequency (highest dual PFD frequency). However, if spur mechanisms are understood, certain combinations of the R-divider and Multiplier can help. Refer to the Optimization of Spurs section for understanding spur types and their mechanisms first, then try this section for these specific spurs.

Moving Phase Detector Frequency

Engaging the multiplier in the reference path allows more flexibility in setting the PFD frequency. One example use case of this is if Fvco % Fpd is the dominant spur. This method can move the PFD frequency and thus the Fvco % Fpd.

Example: Fvco = 3720.12 MHz, Fosc = 300 MHz, Pre-R divider = 5, Fpd = 60 MHz, Fvco%Fosc = 120.12 MHz (Far out), Fvco%Fpd = 120 kHz (dominant). There is a Fvco%Fpd spur at 120 kHz (refer to Figure 27).

LMX2592 multiplier_before.png Figure 27. Fvco % Fpd Spur

Then second case, using divider and multiplier, is Fpd = 53.57 MHz away from 120-kHz spur. Fvco = 3720.12MHz, Fosc = 300MHz, Pre-R divider = 7, Multiplier = 5, Post-R divider = 4, Fpd = 53.57 MHz, Fvco%Fosc = 120.12 MHz (Far out). Fvco % Fpd = 23.79 MHz (far out). There is a 20–dB reduction for the Fvco % Fpd spur at 120 kHz (refer to Figure 28).

LMX2592 multiplier_after.png Figure 28. Moving Away From Fvco % Fpd Spur

Multiplying and Dividing by the Same Value

Although it may not seem like the first thing to try, the Fvco%Fosc and Fout%Fosc spur can sometimes be improved engaging the OSC_2X bit and then dividing by 2. Although this gives the same phase detector frequency, the spur can be improved.

Designing for Output Power

If there is a desired frequency for highest power, use an inductor pullup and design for the value so that the resonance is at that frequency. Use the formula SRF = 1 / (2π× sqrt[L × C]).

Example: C = 1.4 pF (characteristic). If maximum power is targeted at 1 GHz, L = 18 nH. If maximum power is targeted at 3.3 GHz, L = 1.6 nH

LMX2592 output_power_92.gif Figure 29. Output Power vs Pullup Type

Current Consumption Management

The starting point is the typical total current consumption of 250 mA: 100-MHz input frequency, OSCin doubler bypassed, Pre-R divider bypassed, multiplier bypassed, post-R divider bypassed, 100-MHz phase detector frequency, 0.468-mA charge pump current, channel divider off, one output on, 6000-MHz output frequency, 50-Ω output pullup, 0-dBm output power (differential). To understand current consumption changes due to engaging different functional blocks , refer to Table 50.

Table 50. Typical Current Consumption Impact By Function

ACTION STEPS PROGRAMMING INCREASE IN CURRENT (mA)
Use input signal path Enable OSCin doubler OSC_2X = 1 7
Enable multiplier MULT = 3,4,5, or 6 10
Add an output Route VCO to output B VCO_DISTB_PD = 0 8
Enable output B buffer OUTB_PD = 0 54
Increase output power from 0 to +10dBm (differential) Set highest output buffer current OUTA_POW = 63 53
Use channel divider Route channel divider to output CHDIV_DISTA_EN = 1 5
Enable channel divider CHDIV_EN = 1 18
Enable chdiv_seg1 CHDIV_SEG1_EN = 1 2
Enable chdiv_seg2 CHDIV_SEG2_EN = 1 5
Enable chdiv_seg3 CHDIV_SEG3_EN = 1 5
Using VCO doubler Enable VCO doubler VCO2X_EN 16

Decreasing Lock Time

A calibration time of 590 µs typically to lock to 7-GHz VCO can be achieved with default settings as specified in the Electrical Characteristics table. There are several registers that can be programmed to speed up this time. Lock time consists of the calibration time (time required to calibrate the VCO to the correct frequency range) plus the analog settling time (time lock the PLL in phase and frequency). For fast calibration set registers FCAL_FAST = 1 and ACAL_FAST = 1. Also set the calibration clock frequency [input reference frequency] / 2^CAL_CLK_DIV) to 200 MHz. The 20-µs range lock time can be achieved if the amplitude comparator delay is low, set by register ACAL_CMP_DLY (5 in this example). If this is too low there is not enough time to make the decision of VCO amplitude to use and may result in non-optimal phase noise. The other approach is to turn off amplitude calibration with ACAL_EN=0, then manually choose the amplitude with VCO_IDAC (350 for example). This will also result in 20-µs range calibration time. There are many other registers that can aid calibration time, for example ACAL_VCO_IDAC_STRT lets the user choose what VCO amplitude to start with during amplitude calibration. Setting this value to around 350 will give faster times because it is close to the final amplitude for most final frequencies. FCAL_VCO_SEL_START allows you to choose the VCO core to start with for the calibration instead of starting from core 7 by default. If you know you are locking to a frequency around VCO core 1, you can start from VCO 2 by setting VCO_SEL=2, which should give faster lock times. Go to the Register Maps section for detailed information of these registers and their related registers. For fast analog settling time, design loop filter for very wide loop bandwidth (MHz range).

LMX2592 lock_time.gif Figure 30. Lock Time Screenshot

The calibration example as shown in Figure 30 sweeps from the top of the VCO frequency range to the bottom. This example does a calibration to lock at 3.7 GHz (which is longest lock time scenario). For the left screenshot (Wideband Frequency view), see the sweeping from top to bottom of the VCO range. On the right screenshot (Narrowband Frequency view), see the analog settling time to the precise target frequency.

Modeling and Understanding PLL FOM and Flicker Noise

Follow these recommended settings to design for wide loop bandwidth and extract FOM and flicker noise. The flat model is the PLL noise floor modeled by: PLL_flat = PLL_FOM + 20 × log(Fvco/Fpd) + 10 × log(Fpd / 1 Hz). The flicker noise (also known as 1/f noise) which changes by –10dB / decade, is modeled by: PLL_flicker (offset) = PLL_flicker_Norm + 20 × log(Fvco / 1 GHz) – 10 × log(offset / 10k Hz). The cumulative model is the addition of both components: PLL_Noise = 10*log(10PLL_Flat / 10 + 10PLL_flicker / 10). This is adjusted to fit the the measured data to extract the PLL_FOM and PLL_flicker_Norm spec numbers.

Table 51. Wide Loop Filter Design

PARAMETER VALUE
PFD (MHz) 200
Charge pump (mA) 12
VCO frequency (MHz) 5400
Loop bandwidth (kHz) 2000
Phase margin (degrees) 30
Gamma 1.4
Loop filter (2nd order)
C1 (nF) 0.01
C2 (nF) 0.022
R2 (kΩ) 4.7
LMX2592 fom.gif Figure 31. FOM and Flicker Noise Modeling

Typical Application

Design for Low Jitter

LMX2592 lmx25xx_typical_application_schematic_snas646.gif Figure 32. Typical Application Schematic

Design Requirements

Refer to the design parameters shown in Table 52.

Table 52. Design Information

PARAMETER VALUE
PFD (MHz) 200
Charge pump (mA) 20
VCO frequency (MHz) 6000
Loop bandwidth (kHz) 210
Phase margin (degrees) 70
Gamma 3.8
Loop filter (2nd order)
C1 (nF) 4.7
C2 (nF) 100
R2 (Ω) 68

Detailed Design Procedure

The integration of phase noise over a certain bandwidth (jitter) is an performance specification that translates to signal-to-noise ratio. Phase noise inside the loop bandwidth is dominated by the PLL, while the phase noise outside the loop bandwidth is dominated by the VCO. As a rule of thumb, jitter is lowest if loop bandwidth is designed to the point where the two intersect. A higher phase margin loop filter design has less peaking at the loop bandwidth and thus lower jitter. The tradeoff with this as longer lock times and spurs should be considered in design as well.

Application Curve

LMX2592 jitter_6G.png
Figure 33. Typical Jitter