SNAS646F December   2015  – November 2017 LMX2592

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Functional Description
      1. 7.3.1  Input Signal
      2. 7.3.2  Input Signal Path
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
      5. 7.3.5  Voltage Controlled Oscillator
      6. 7.3.6  VCO Calibration
      7. 7.3.7  VCO Doubler
      8. 7.3.8  Channel Divider
      9. 7.3.9  Output Distribution
      10. 7.3.10 Output Buffer
      11. 7.3.11 Phase Adjust
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Lock Detect
      3. 7.4.3 Register Readback
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1 LMX2592 Register Map - Default Values
        1. 7.6.1.1 Register Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Optimization of Spurs
        1. 8.1.1.1 Understanding Spurs by Offsets
        2. 8.1.1.2 Spur Mitigation Techniques
      2. 8.1.2 Configuring the Input Signal Path
        1. 8.1.2.1 Input Signal Noise Scaling
      3. 8.1.3 Input Pin Configuration
      4. 8.1.4 Using the OSCin Doubler
      5. 8.1.5 Using the Input Signal Path Components
        1. 8.1.5.1 Moving Phase Detector Frequency
        2. 8.1.5.2 Multiplying and Dividing by the Same Value
      6. 8.1.6 Designing for Output Power
      7. 8.1.7 Current Consumption Management
      8. 8.1.8 Decreasing Lock Time
      9. 8.1.9 Modeling and Understanding PLL FOM and Flicker Noise
    2. 8.2 Typical Application
      1. 8.2.1 Design for Low Jitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHA|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description

Overview

The LMX2592 is a high performance wideband synthesizer (PLL with integrated VCO). The output frequency range is from 20 MHz to 9.5 GHz. The VCO core covers an octave from 3.55 to 7.1 GHz. The output channel divider covers the frequency range from 20 MHz to the low bound of the VCO core. The VCO-doubler covers the frequency range from the upper bound of the VCO to 9800MHz.

The input signal frequency has a wide range from 5 to 1400 MHz. Following the input, there is an programmable OSCin doubler, a pre-R divider (previous to multiplier), a multiplier, and then a post-R divider (after multiplier) for flexible frequency planning between the input (OSCin) and the phase detector.

The phase detector (PFD) can take frequencies from 5 to 200 MHz, but also has extended modes down to 0.25 MHz and up to 400 MHz. The phase-lock loop (PLL) contains a Sigma-Delta modulator (1st to 4th order) for fractional N-divider values. The fractional denominator is programmable to 32-bit long, allowing a very fine resolution of frequency step. There is a phase adjust feature that allows shifting of the output phase in relation to the input (OSCin) by a fraction of the size of the fractional denominator.

The output power is programmable and can be designed for high power at a specific frequency by the pullup component at the output pin.

The digital logic is a standard 4-wire SPI or uWire interface and is 1.8-V and 3.3-V compatible.

Functional Block Diagram

LMX2592 functional_diagram.gif

Functional Description

Input Signal

An input signal is required for the PLL to lock. The input signal is also used for the VCO calibration, so a proper signal needs to be applied before the start of programming. The input signal goes to the OSCinP and OSCinM pins of the device (there is internal biasing which requires AC-coupling caps in series before the pin). This is a differential buffer so the total swing is the OSCinM signal subtracted by the OSCinP signal. Both differential signals and single-ended signal can be used. Below is an example of the max signal level in each mode. It is important to have proper termination and matching on both sides (see Application and Implementation).

LMX2592 input_signal_box.gif Figure 18. Differential vs Single-Ended Mode

Input Signal Path

The input signal path contains the components between the input (OSCin) buffer and the phase detector. The best PLL noise floor is achieved with a 200-MHz input signal for the highest dual-phase detector frequency. To address a wide range of applications, the input signal path contains the below components for flexible configuration before the phase detector. Each component can be bypassed. See Table 1 for usage boundaries if engaging a component.

  • OSCin doubler: This is low noise frequency doubler which can be used to multiply input frequencies by two. The doubler uses both the rising and falling edge of the input signal so the input signal must have 50% duty cycle if enabling the doubler. The best PLL noise floor is achieved with 200-MHz PFD, thus the doubler is useful if, for example, a very low-noise, 100-MHz input signal is available instead.
  • Pre-R divider: This is a frequency divider capable of very high frequency inputs. Use this to divide any input frequency up to 1400-MHz, and then the post-R divider if lower frequencies are needed.
  • Multiplier: This is a programmable, low noise multiplier. In combination with the Pre-R and Post-R dividers, the multiplier offers the flexibility to set a PFD away from frequencies that may create critical integer boundary spurs with the VCO and output frequencies. See the Application and Implementation section for an example. The user should not use the doubler while using the low noise programmable multiplier.
  • Post-R divider: Use this divider to divide down to frequencies below 5 MHz in extended PFD mode.

Table 1. Boundaries for Input Path Components

INPUT OUTPUT
LOW (MHz) HIGH (MHz) LOW (MHz) HIGH (MHz)
Input signal 5 1400
OSCin doubler 5 200 10 400
Pre-R divider 10 1400 5 700
Multiplier 40 70 180 250
Post-R divider 5 250 0.25 125
PFD 0.25 400

PLL Phase Detector and Charge Pump

The PLL phase detector, also known as phase frequency detector (PFD), compares the outputs of the post-R divider and N divider and generates a correction current with the charge pump corresponding to the phase error until the two signals are aligned in phase (the PLL is locked). The charge pump output goes through external components (loop filter) which turns the correction current pulses into a DC voltage applied to the tuning voltage (Vtune) of the VCO. The charge pump gain level is programmable and allow to modify the loop bandwdith of the PLL.

The default architecture is a dual-loop PFD which can operate between 5 to 200 MHz. To use it in extended range mode the PFD has to be configured differently:

  • Extended low phase detector frequency mode: For frequencies between 250 kHz and 5 MHz, low PFD mode can be activated (FCAL_LPFD_ADJ = 3). PLL_N_PRE also needs to be set to 4.
  • Extended high phase detector frequency mode: For frequencies between 200 and 400 MHz, high PFD mode can be activated (FCAL_HPFD_ADJ = 3). The PFD also has to be set to single-loop PFD mode (PFD_CTL = 3). This mode only works if using integer-N, and PLL noise floor will be about 6-dB higher than in dual-loop PFD mode.

N Divider and Fractional Circuitry

The N divider (12 bits) includes a multi-stage noise shaping (MASH) sigma-delta modulator with programmable order from 1st to 4th order, which performs fractional compensation and can achieve any fractional denominator from 1 to (232 – 1). Using programmable registers, PLL_N is the integer portion and PLL_NUM / PLL_DEN is the fractional portion, thus the total N divider value is determined by PLL_N + PLL_NUM / PLL_DEN. This allows the output frequency to be a fractional multiplication of the phase detector frequency. The higher the denominator the finer the resolution step of the output. There is a N divider prescalar (PLL_N_PRE) between the VCO and the N divider which performs a division of 2 or 4. 2 is selected typically for higher performance in fractional mode and 4 may be desirable for lower power operation and when N is approaching max value.

Fvco = Fpd × PLL_N_PRE × (PLL_N + PLL_NUM / PLL_DEN)

Minimum output frequency step = Fpd × PLL_N_PRE / PLL_DEN / [Channel divider value]

Typically, higher modulator order pushes the noise out in frequency and may be filtered out with the PLL. However, several tradeoff needs to be made. Table 2 shows the suggested minimum N value while in fractional mode as a function of the sigma-delta modulator order. It also describe the recommended register setting for the PFD delay (register PFD_DLY_SEL).

Table 2. MASH Order and N Divider

INTEGER-N 1st ORDER 2nd ORDER 3rd ORDER 4th ORDER
Minimum N divider (low bound) 9 11 16 18 30
PFD delay recommended setting (PFD_DLY_SEL) 1 1 2 2 8

Voltage Controlled Oscillator

The voltage controlled oscillator (VCO) is fully integrated. The frequency range of the VCO is from 3.55 to 7.1 GHz so it covers one octave. Channel dividers allow the generation of all other lower frequencies. The VCO-doubler allow the generation of all other higher frequencies. The output frequency of the VCO is inverse proportional to the DC voltage present at the tuning voltage point on pin Vtune. The tuning range is 0 V to 2.5 V. 0 V generates the maximum frequency and 2.5 V generates the minimum frequency. This VCO requires a calibration procedure for each frequency selected to lock on. Each VCO calibration will force the tuning voltage to mid value and calibrate the VCO circuit. Any frequency setting in fast calibration occurs in the range of Vtune pin 0 V to 2.5 V. The VCO is designed to remained locked over the entire temperature range the device can support. Table 3 shows the VCO gain as a function of frequency.

Table 3. Typical kVCO

VCO FREQUENCY (MHz) kVCO (MHz/V)
3700 28
4200 30
4700 33
5200 36
5700 41
6200 47
6800 51

VCO Calibration

The VCO calibration is responsible of setting the VCO circuit to the target frequency. The frequency calibration routine is activated any time that the R0 register is programmed with the FCAL_EN = 1. A valid input (OSCin) signal to the device must present before the VCO calibration begins. To see how to reduce the calibration time, refer to the Application and Implementation section.

VCO Doubler

To go above the VCO upper bound, the VCO-doubler must be used (VCO_2X_EN=1). The doubling block can be enabled while the VCO is between 3.55 GHz (lowest VCO frequency) and 4.9 GHz. When VCO doubler is enabled, the N divider prescalar is automatically forced to divide by 4.

Channel Divider

LMX2592 channel_divider.gif Figure 19. Channel Divider Diagram

To go below the VCO lower bound, the channel divider must be used. The channel divider consists of three programmable dividers controlled by the registers CHDIV_SEG1, CHDIV_SEG2, CHDIV_SEG3. The Multiplexer (programmed with register CHDIV_SEG_SEL) selects which divider is included in the path. The minimum division is 2 while the maximum division is 192. Un-used dividers can be powered down to save current consumption. The entire channel divider can be powered down with register CHDIV_EN = 0 or selectively setting registers CHDIV_SEG1_EN = 0, CHDIV_SEG2_EN = 0 ,CHDIV_SEG3_EN = 0. Unused buffers may also be powered down with registers CHDIV_DISTA_EN and CHDIV_DIST_EN. See Table 4 for a guideline of what channel divider setting to use when below a specific output frequency.

Table 4. Channel Divider Setting as a Function of the Desired Output Frequency

Output Frequency CHDIV Segments VCO Frequency
min max seg1 seg2 seg3 total div min max
1775 3550 2 1 1 2 3550 7100
1184 2366.666667 3 1 1 3 3552 7100
888 1184 2 2 1 4 3552 4736
592 888 3 2 1 6 3552 5328
444 592 2 4 1 8 3552 4736
296 444 2 6 1 12 3552 5328
222 296 2 8 1 16 3552 4736
148 222 3 8 1 24 3552 5328
111 148 2 8 2 32 3552 4736
99 111 3 6 2 36 3564 3996
74 99 3 8 2 48 3552 4752
56 74 2 8 4 64 3584 4736
37 56 2 8 6 96 3552 5376
28 37 2 8 8 128 3584 4736
20 28 3 8 8 192 3840 5376

Output Distribution

LMX2592 output_distribution_flip.gif Figure 20. Output Distribution Diagram

For each output A or B, there is a mux which select the VCO output directly or the channel divider output. Before these selection MUX there are several buffers in the distribution path which can be configured depending on the route selected. By disabling unused buffers, unwanted signals can be isolated and unneeded current consumption can be eliminated.

Output Buffer

Each output buffer (A and B) have programmable gain with register OUTA_POW and OUTB_POW. The RF output buffer configuration is open-collector and requires an external pullup from RFout pin to VCC. There are two pullup options that can be used with either resistor or inductor. Refer to the Application and Implementation section for design considerations.

  1. Resistor pullup: placing a 50-Ω resistor pullup matches the output impedance to 50-Ω. However, maximum output power is limited. Output buffer current settings should be set to a value before output power is saturated (output power increases less for every step increase in output current value).
  2. Inductor pullup: placing an inductor pullup creates a resonance at the frequency of interest. This offers higher output power for the same current and higher maximum output power. However, the output impedance is higher and additional matching may be required..

Phase Adjust

In fractional mode, the phase relationship between the output and the input can be changed with very fine resolution. Every time MASH_SEED register is written, it will trigger a phase shift of the amount described in Equation 1. The seed value should be less then the fractional-N denominator register PLL_N_DEN. The actual phase shift can be obtained with the following equation:

Equation 1. Phase shift (degrees) = 360 × MASH_SEED × PLL_N_PRE / PLL_N_DEN / [Channel divider value]

Device Functional Modes

Power Down

Power up and down can be achieved using the CE pin (logic HIGH or LOW voltage) or the POWERDOWN register bit (0 or 1). When the device comes out of the powered-down state, either by pulling back CE pin HIGH (if it was powered down by CE pin) or by resuming the POWERDOWN bit to 0 (if it was powered down by register write), it is required that register R0 be programmed again to re-calibrate the device.

Lock Detect

The MUXout pin can be configured to output a signal that gives an indication for the PLL being locked. If lock detect is enabled (LD_EN = 1) and the MUXout pin is configured as lock detect output (MUXOUT_SEL = 1), when the device is locked, the MUXout pin output is a logic HIGH voltage, and when the device is unlocked, MUXout output is a logic LOW voltage.

Register Readback

The MUXout pin can be programmed (MUXOUT_SEL = 0) to use register readback serial data output. Timing requirements for MUXout to CLK follow the same specifications as Data to CLK in Timing Requirements. To read back a certain register value, use the following steps:

  1. Set the R/W bit to 1; the data field contents are ignored.
  2. Program this register to the device, readback serial data will be output starting at the 9th clock.
LMX2592 readback_diagram.gif Figure 21. Register Readback Timing Diagram

Programming

The programming using 24-bit shift registers. The shift register consists of a R/W bit (MSB), followed by a 7-bit address field and a 16-bit data field. For the R/W (bit 23), 1 is read and 0 is write. The address field ADDRESS (bits 22:16) is used to decode the internal register address. The remaining 16 bits form the data field DATA (bits 15:0). While CSB is low, serial data is clocked into the shift register upon the rising edge of clock (data is programmed MSB first). When CSB goes high, data is transferred from the data field into the selected register bank.

Recommended Initial Power on Programming Sequence

When the device is first powered up, the device needs to be initialized and the ordering of this programming is very important. After this sequence is completed, the device should be running and locked to the proper frequency.

  1. Apply power to the device and ensure the VCC pins are at the proper levels
  2. Ensure that a valid reference is applied to the OSCin pin
  3. Soft reset the device (write R0[1] = 1)
  4. Program the remaining registers
  5. Frequency calibrate (write R0[3] = 1)

Recommended Sequence for Changing Frequencies

The recommended sequence for changing frequencies is as follows:

  1. Set the new N divider value (write R38[12:1])
  2. Set the new PLL numerator (R45 and R44) and denominator (R41 and R40)
  3. Frequency calibrate (write R0[3] = 1)

Register Maps

LMX2592 Register Map – Default Values

Figure 22. Register Table
REG 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W ADDRESS[6:0] DATA [15:0]
0 R/W 0 0 0 0 0 0 0 0 0 LD_EN 0 0 0 1 FCAL_HPFD_ADJ FCAL_LPFD_ADJ ACAL_EN FCAL_EN MUXOUT_SEL RESET POWERDOWN
1 R/W 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 CAL_CLK_DIV
2 R/W 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0
4 R/W 0 0 0 0 1 0 0 ACAL_CMP_DLY 0 1 0 0 0 0 1 1
7 R/W 0 0 0 0 1 1 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0
8 R/W 0 0 0 1 0 0 0 0 0 VCO_IDAC_OVR 1 0 VCO_CAPCTRL_OVR 0 0 1 0 0 0 0 1 0 0
9 R/W 0 0 0 1 0 0 1 0 0 0 0 OSC_2X 0 REF_EN 1 0 0 0 0 0 0 1 0
10 R/W 0 0 0 1 0 1 0 0 0 0 1 MULT 1 0 1 1 0 0 0
11 R/W 0 0 0 1 0 1 1 0 0 0 0 PLL_R 1 0 0 0
12 R/W 0 0 0 1 1 0 0 0 1 1 1 PLL_R_PRE
13 R/W 0 0 0 1 1 0 1 0 CP_EN 0 0 0 0 PFD_CTL 0 0 0 0 0 0 0 0
14 R/W 0 0 0 1 1 1 0 0 0 0 0 CP_IDN CP_IUP CP_ICOARSE
19 R/W 0 0 1 0 0 1 1 0 0 0 0 VCO_IDAC 1 0 1
20 R/W 0 0 1 0 1 0 0 0 0 0 0 0 0 0 ACAL_VCO_IDAC_STRT
22 R/W 0 0 1 0 1 1 0 0 0 1 0 0 0 1 1 VCO_CAPCTRL
23 R/W 0 0 1 0 1 1 1 1 FCAL_VCO_SEL_STRT VCO_SEL VCO_SEL_FORCE 0 0 0 1 0 0 0 0 1 0
24 R/W 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1
25 R/W 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
28 R/W 0 0 1 1 1 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0
29 R/W 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0
30 R/W 0 0 1 1 1 1 0 0 0 0 0 0 MASH_DITHER 0 0 0 0 1 1 0 1 0 VCO_2X_EN
31 R/W 0 0 1 1 1 1 1 0 0 0 0 0 VCO_DISTB_PD VCO_DISTA_PD 0 CHDIV_DIST_PD 0 0 0 0 0 0 1
32 R/W 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0
33 R/W 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0
34 R/W 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 1 1 CHDIV_EN 0 1 0 1 0
35 R/W 0 1 0 0 0 1 1 0 0 0 CHDIV_SEG2 CHDIV_SEG3_EN CHDIV_SEG2_EN 0 0 1 1 CHDIV_SEG1 CHDIV_SEG1_EN 1
36 R/W 0 1 0 0 1 0 0 0 0 0 0 CHDIV_DISTB_EN CHDIV_DISTA_EN 0 0 0 CHDIV_SEG_SEL CHDIV_SEG3
37 R/W 0 1 0 0 1 0 1 0 1 0 PLL_N_PRE 0 0 0 0 0 0 0 0 0 0 0 0
38 R/W 0 1 0 0 1 1 0 0 0 0 PLL_N 0
39 R/W 0 1 0 0 1 1 1 1 0 PFD_DLY 0 0 0 0 0 1 0 0
40 R/W 0 1 0 1 0 0 0 PLL_DEN[31:16]
41 R/W 0 1 0 1 0 0 1 PLL_DEN[15:0]
42 R/W 0 1 0 1 0 1 0 MASH_SEED[31:16]
43 R/W 0 1 0 1 0 1 1 MASH_SEED[15:0]
44 R/W 0 1 0 1 1 0 0 PLL_NUM[31:16]
45 R/W 0 1 0 1 1 0 1 PLL_NUM[15:0]
46 R/W 0 1 0 1 1 1 0 0 0 OUTA_POW OUTB_PD OUTA_PD 1 0 0 MASH_ORDER
47 R/W 0 1 0 1 1 1 1 0 0 0 OUTA_MUX 0 0 0 1 1 OUTB_POW
48 R/W 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OUTB_MUX
59 R/W 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 MUXOUT_HDRV 0 0 0 0 0
61 R/W 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LD_TYPE
62 R/W 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
64 R/W 1 0 0 0 0 0 0 0 0 0 0 0 0 ACAL_FAST FCAL_FAST AJUMP_SIZE 1 FJUMP_SIZE

Register Descriptions

Table 5. R0 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:14 R/W Program to Regist.er Map default values
13 LD_EN R/W 1 Lock detect enable
1: enable
0: disable
12:9 R/W Program to Register Map default values
8:7 FCAL_HPFD_ADJ R/W 0 Used for when PFD freq is high
3: PFD > 200 MHz
2: PFD > 150 MHz
1: PFD > 100 MHz
0: not used
6:5 FCAL_LPFD_ADJ R/W 0 Used for when PFD freq is low
3: PFD < 5 MHz
2: PFD < 10 MHz
1: PFD < 20 MHz
0: not used
4 ACAL_EN R/W 1 Enable amplitude calibration
1: enable (calibration algorithm will set VCO amplitude. For manual mode set register VCO_IDAC_OVR=1, and then set the VCO amplitude by register VCO_IDAC)
0: disable
3 FCAL_EN R/W 1 Enable frequency calibration
1: enable (writing 1 to this register triggers the calibration sequence)
0: disable
2 MUXOUT_SEL R/W 1 Signal at MUXOUT pin
1: Lock Detect (3.3 V if locked, 0 V if unlocked)
0: Readback (3.3-V digital output)
1 RESET R/W 0 Reset
Write with a value of 1 to reset device (this register will self-switch back to 0)
0 POWERDOWN R/W 0 Powerdown whole device
1: power down
0: power up

Table 6. R1 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:3 R/W Program to Register Map default values
2:0 CAL_CLK_DIV R/W 3 Divides down the OSCin signal for calibration clock
Calibration Clock = OSCin / 2^CAL_CLK_DIV
Set this value so that calibration clock is less than but as close to 200MHz as possible if fast calibration time is desired.

Table 7. R2 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:0 R/W Program to Register Map default values

Table 8. R4 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:8 ACAL_CMP_DLY R/W 25 VCO amplitude calibration delay. Lowering this value can speed calibration time. The guideline for this register is 2 x [ACAL_CMP_DLY value] x [calibration clock period] > 200ns. As described in CAL_CLK_DIV, the calibration clock is defined as OSCin / 2^CAL_CLK_DIV. For example, with the fastest calibration clock of 200MHz (OSCin=200MHz and CAL_CLK_DIV=0), the period is 5ns. So ACAL_CMP_DLY should be > 20. With the same derivation, an example of a OSCin=100MHz, ACAL_CMP_DLY should be > 10. This register is left at a default value of 25 if there is no need to shorten calibration time.
7:0 R/W Program to Register Map default values

Table 9. R7 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:0 R/W Program to Register Map default values

Table 10. R8 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:14 R/W Program to Register Map default values
13 VCO_IDAC_OVR R/W 0 This is the over-ride bit for VCO amplitude (or IDAC value). When this is enabled, the VCO amplitude calibration function (ACAL_EN) is not used. VCO_IDAC register can be programmed to set the amplitude. Keep the VCO_IDAC value within 250 and 450.
12:11 R/W Program to Register Map default values
10 VCO_CAPCTRL_OVR R/W 0 This is the over-ride bit for VCO capacitor bank code (or CAPCTRL value). When this is enabled, the VCO frequency calibration function (FCAL_EN) is not used. the VCO_CAPCTRL register can be programmed to set the VCO frequency within the selected VCO core. The VCO core is selected by setting VCO_SEL_FORCE=1 and then selecting the core with VCO_SEL=1,2,3,4,5,6, or 7
9:0 R/W Program to Register Map default values

Table 11. R9 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:12 R/W Program to Register Map default values
11 OSC_2X R/W 0 Reference path doubler
1: enable
0: disable
10 R/W Program to Register Map default values
9 REF_EN R/W 1 Enable reference path
1: enable
0: disable
8:0 R/W Program to Register Map default values

Table 12. R10 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:12 R/W Program to Register Map default values
11:7 MULT R/W 1 Input signal path multiplier (input range from 40 - 70 MHz, output range from 180 - 250 MHz)
6:0 R/W Program to Register Map default values

Table 13. R11 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:12 R/W Program to Register Map default values
11:4 PLL_R R/W 1 R divider after multiplier and before PFD
3:0 R/W Program to Register Map default values

Table 14. R12 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:12 R/W Program to Register Map default values
11:0 PLL_R_PRE R/W 1 R divider after OSCin doubler and before multiplier

Table 15. R13 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15 R/W Program to Register Map default values
14 CP_EN R/W 1 Enable charge pump
1: enable
0: disable
13:10 R/W Program to Register Map default values
9:8 PFD_CTL R/W 0 PFD mode
0: Dual PFD (default)
3: Single PFD (ONLY use if PFD freq is higher than 200MHz)
7:0 R/W Program to Register Map default values

Table 16. R14 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:12 R/W Program to Register Map default values
11:7 CP_IDN R/W 3 Charge pump current (DN) – must equal to charge pump current (UP). Can activate any combination of bits.
<bit 4>: 1.25 mA
<bit 3>: 2.5 mA
<bit 2>: 0.625 mA
<bit 1>: 0.312 mA
<bit 0>: 0.156 mA
6:2 CP_IUP R/W 3 Charge pump current (UP) – must equal to charge pump current (DN). Can activate any combination of bits.
<bit 4>: 1.25 mA
<bit 3>: 2.5 mA
<bit 2>: 0.625 mA
<bit 1>: 0.312 mA
<bit 0>: 0.156 mA
1:0 CP_ICOARSE R/W 1 charge pump gain multiplier - multiplies charge pump current by a given factor:
3: multiply by 2.5
2: multiply by 1.5
1: multiply by 2
0: no multiplication

Table 17. R19 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:12 R/W Program to Register Map default values
11:3 VCO_IDAC R/W 300 This is the VCO amplitude (or IDAC value). When VCO_IDAC is over-riden with VCO_IDAC_OVR=1, VCO amplitude calibration function (ACAL_EN) is not used. VCO_IDAC register can be programmed to set the amplitude. VCO_IDAC value must be kept within 250 and 450.
2:0 R/W Program to Register Map default values

Table 18. R20 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:9 R/W Program to Register Map default values
8:0 ACAL_VCO_IDAC_STRT R/W 300 This register is used to aid the VCO amplitude calibration function (ACAL_EN). By default the amplitude calibration function searches from the low end of VCO_IDAC until it reaches the target value. Like the VCO_IDAC, this must be kept within 250 and 450. This can be set to a value closer to the target value, then the amplitude calibration time can be shortened typically final VCO_IDAC is somewhere around 300.

Table 19. R22 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:8 R/W Program to Register Map default values
7:0 VCO_CAPCTRL R/W 0 This is the VCO capacitor bank code (or CAPCTRL value). When VCO_CAPCTRL is over-riden with VCO_CAPCTRL_OVR=1, VCO frequency calibration function (FCAL_EN) is not used. VCO_CAPCTRL register can be programmed to set the frequency in that core. VCO_SEL_FORCE=1 has to be set and VCO_SEL to select the VCO core, then CAPCTRL values between 0 to 183 will produce frequencies within this core (0 being the highest frequency and 183 the lowest).

Table 20. R23 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15 R/W Program to Register Map default values
14 FCAL_VCO_SEL_STRT R/W 0 This is a register that aids the frequency calibration function. When this is enabled, a VCO core can be selected for the frequency calibration to start at, set by register VCO_SEL. By default the frequency calibration starts from VCO core 7 and works its way down. If you want for example to lock to a frequency in VCO core 1, you can set VCO_SEL to 2, so the calibration will start at VCO core 2 and end at target frequency at VCO core 1 faster.
13:11 VCO_SEL R/W 1 This is the register used to select VCO cores. It works for VCO_CAPCTRL when VCO_CAPCTRL_OVR=1 and VCO_SEL_FORCE=1. It also aids the frequency calibration function with FCAL_VCO_SEL_STRT.
10 VCO_SEL_FORCE R/W 0 This register works to force selection of VCO cores. If VCO_CAPTRL_OVR=1 and this register is enabled, you can select the VCO core to use with VCO_SEL.
9:0 R/W Program to Register Map default values

Table 21. R24 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:0 R/W Program to default

Table 22. R25 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:0 R/W Program to Register Map default values

Table 23. R28 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:0 R/W Program to Register Map default values

Table 24. R29 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:0 R/W Program to Register Map default values

Table 25. R30 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:11 R/W Program to Register Map default values
10 MASH_DITHER R/W 0 MASH dithering: toggle on/off to randomize
9:1 R/W Program to Register Map default values
0 VCO_2X_EN R/W 0 Enable VCO doubler
1: enable
0: disable

Table 26. R31 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:11 R/W Program to Register Map default values
10 VCO_DISTB_PD R/W 1 Power down buffer between VCO and output B
1: power down
0: power up
9 VCO_DISTA_PD R/W 0 Power down buffer between VCO and output A
1: power down
0: power up
8 R/W Program to Register Map default values
7 CHDIV_DIST_PD R/W 0 Power down buffer between VCO and channel divider
6:0 R/W Program to Register Map default values

Table 27. R32 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:0 R/W Program to Register Map default values

Table 28. R33 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:0 R/W Program to Register Map default values

Table 29. R34 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:6 R/W Program to Register Map default values
5 CHDIV_EN R/W 1 Enable entire channel divider
1: enable
0: power down
4:0 R/W Program to Register Map default values

Table 30. R35 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:13 R/W Program to Register Map default values
12:9 CHDIV_SEG2 R/W 1 Channel divider segment 2
8: divide-by-8
4: divide-by-6
2: divide-by-4
1: divide-by-2
0: PD
8 CHDIV_SEG3_EN R/W 0 Channel divider segment 3
1: enable
0: power down (power down if not needed)
7 CHDIV_SEG2_EN R/W 0 Channel divider segment 2
1: enable
0: power down (power down if not needed)
6:3 R/W Program to Register Map default values
2 CHDIV_SEG1 R/W 1 Channel divider segment 1
1: divide-by-3
0: divide-by-2
1 CHDIV_SEG1_EN R/W 0 Channel divider segment 1
1: enable
0: power down (power down if not needed)
0 R/W Program to Register Map default values

Table 31. R36 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:12 R/W Program to Register Map default values
11 CHDIV_DISTB_EN R/W 0 Enable buffer between channel divider and output B
1: enable
0: disable
10 CHDIV_DISTA_EN R/W 1 Enable buffer between channel divider and output A
1: enable
0: disable
9:7 R/W Program to Register Map default values
6:4 CHDIV_SEG_SEL R/W 1 Channel divider segment select
4: includes channel divider segment 1,2 and 3
2: includes channel divider segment 1 and 2
1: includes channel divider segment 1
0: PD
3:0 CHDIV_SEG3 R/W 1 Channel divider segment 3
8: divide-by-8
4: divide-by-6
2: divide-by-4
1: divide-by-2
0: PD

Table 32. R37 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:13 R/W Program to Register Map default values
12 PLL_N_PRE R/W 0 N-divider pre-scalar
1: divide-by-4
0: divide-by-2
11:0 R/W Program to Register Map default values

Table 33. R38 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:13 R/W Program to Register Map default values
12:1 PLL_N R/W 27 Integer part of N-divider
0 R/W Program to Register Map default values

Table 34. R39 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:14 R/W Program to Register Map default values
13:8 PFD_DLY R/W 2 PFD Delay
32: Not used
16: 16 clock cycle delay
8: 12 clock cycle delay
4: 8 clock cycle delay
2: 6 clock cycle delay
1: 4 clock cycle delay
7:0 R/W Program to Register Map default values

Table 35. R40 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:0 PLL_DEN[31:16] R/W 1000 Denominator MSB of N-divider fraction

Table 36. R41 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:0 PLL_DEN[15:0] R/W 1000 Denominator LSB of N-divider fraction

Table 37. R42 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:0 MASH_SEED[31:16] R/W 0 MASH seed MSB

Table 38. R43 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:0 MASH_SEED[15:0] R/W 0 MASH seed LSB

Table 39. R44 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:0 PLL_NUM[31:16] R/W 0 Numerator MSB of N-divider fraction

Table 40. R45 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:0 PLL_NUM[15:0] R/W 0 Numerator LSB of N-divider fraction

Table 41. R46 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15 R/W Program to Register Map default values
13:8 OUTA_POW R/W 15 Output buffer A power
increase power from 0 to 31
extra boost from 48 to 63
7 OUTB_PD R/W 1 Output buffer B power down
1: power down
0: power up
6 OUTA_PD R/W 0 Output buffer A power down
1: power down
0: power up
5:3 R/W Program to Register Map default values
2:0 MASH_ORDER R/W 3 Sigma-delta modulator order
4: fourth order
3: third order
2: second order
1: first order
0: integer mode

Table 42. R47 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:13 R/W Program to Register Map default values
12:11 OUTA_MUX R/W 0 Selects signal to the output buffer
2,3: reserved
1: Selects output from VCO
0: Selects the channel divider output
10:6 R/W Program to Register Map default values
5:0 OUTB_POW R/W 0 Output buffer B power
increase power from 0 to 31
extra boost from 48 to 63

Table 43. R48 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:2 R/W Program to Register Map default values
1:0 OUTB_MUX R/W 0 Selects signal to the output buffer
2,3: reserved
1: Selects output from VCO
0: Selects the channel divider output

Table 44. R59 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:6 R/W Program to Register Map default values
5 MUXOUT_HDRV R/W 0 This bit enables higher current output at MUXOUT pin if value is 1.
4:0 R/W Program to Register Map default values

Table 45. R61 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:1 R/W Program to Register Map default values
0 LD_TYPE R/W 1 To use lock detect, set MUXOUT_SEL=1. Use this register to select type of lock detect:
0: Calibration status detect (this indicates if the auto-calibration process has completed successfully and will output from MUXout pin a logic HIGH when successful). 1: vtune detect (this checks if vtune is in the expected range of voltages and outputs from MUXout pin a logic HIGH if device is locked and LOW if unlocked).

Table 46. R62 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:0 R/W Program to Register Map default values

Table 47. R64 Register Field Descriptions

BIT FIELD TYPE DEFAULT DESCRIPTION
15:10 R/W Program to Register Map default values
9 ACAL_FAST R/W 0 Enable fast amplitude calibration
1: enable
0: disable
8 FCAL_FAST R/W 0 Enable fast frequency calibration
1: enable
0: disable
7:5 AJUMP_SIZE R/W 3 When ACAL_FAST=1, use this register to select the jump increment
4 R/W Program to Register Map default values
3:0 FJUMP_SIZE R/W 15 When FCAL_FAST=1, use this register to select the jump increment