SNVS550E September   2009  – January 2017 LP5523

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Charge Pump Electrical Characteristics
    7. 6.7  LED Driver Electrical Characteristics
    8. 6.8  LED Test Electrical Characteristics
    9. 6.9  Logic Interface Characteristics
    10. 6.10 Recommended External Clock Source Conditions
    11. 6.11 Serial Bus Timing Parameters (SDA, SCL)
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Programming
      2. 7.3.2 LED Error Detection
      3. 7.3.3 Energy Efficiency
      4. 7.3.4 Temperature Compensation
      5. 7.3.5 Charge Pump Operational Description
        1. 7.3.5.1 Overview
        2. 7.3.5.2 Output Resistance
        3. 7.3.5.3 Controlling The Charge Pump
        4. 7.3.5.4 LED Forward Voltage Monitoring
        5. 7.3.5.5 Gain Change Hysteresis
      6. 7.3.6 LED Driver Operational Description
        1. 7.3.6.1 Overview
        2. 7.3.6.2 Powering LEDs
        3. 7.3.6.3 Controlling The High-Side LED Drivers
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes Of Operation
        1. 7.4.1.1 Automatic Power-Save Mode
        2. 7.4.1.2 PWM Power-Save Mode
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Control Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
          1. 7.5.1.4.1 Control Register Write Cycle
          2. 7.5.1.4.2 Control Register Read Cycle
          3. 7.5.1.4.3 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Set
      2. 7.6.2 Control Register Details
      3. 7.6.3 Instruction Set
      4. 7.6.4 LED Driver Instructions
        1. 7.6.4.1 Ramp
        2. 7.6.4.2 Ramp Instruction Application Example
        3. 7.6.4.3 Set_PWM
        4. 7.6.4.4 Wait
      5. 7.6.5 LED Mapping Instructions
      6. 7.6.6 Branch Instructions
      7. 7.6.7 Arithmetic Instructions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Using Two LP5523 Devices in Same Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Recommended External Components
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Driving Haptic Feedback with LP5523
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN MAX UNIT
VDD –0.3 6 V
Voltage on D1 to D9, C1−, C1+, C2–, C+, VOUT –0.3 VDD + 0.3 V with 6 V maximum V
Continuous power dissipation Internally limited
Junction temperature, TJ-MAX 125 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications.
(3) All voltages are with respect to the potential at the GND pin.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins except D1 to D9 ±2500 V
Pins D1 to D9 ±8000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) All pins ±1000
Machine model All pins 250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VDD input voltage 2.7 5.5 V
Voltage on logic pins (input or output pins) 0 VDD V
Recommended charge pump load current 0 100 mA
Junction temperature, TJ –30 125 °C
Ambient temperature, TA (2) –30 85 °C
(1) All voltages are with respect to the potential at the GND pin.
(2) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).

6.4 Thermal Information

THERMAL METRIC(1) LP5523 UNIT
YFQ (DSBGA)
25 PINS
RθJA(2) Junction-to-ambient thermal resistance 60.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.4 °C/W
RθJB Junction-to-board thermal resistance 9.9 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 10.0 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.

6.5 Electrical Characteristics

Unless otherwise noted: typical limits are for TA = 25°C; minimum and maximum limits apply over the operating ambient temperature range (−30°C < TA < +85°C), specifications apply to the Functional Block Diagram with: VDD = 3.6 V, VEN = 1.65 V, COUT = 1 µF, CIN = 1 µF, C1–2 = 0.47 µF.(1)(2)(3)(4)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IVDD Standby supply current VEN = 0V, CHIP_EN=0 (bit), external 32-kHz clock running or not running 0.2 µA
CHIP_EN=0 (bit), external 32 kHz clock not running 1 µA
CHIP_EN=0 (bit), external 32 kHz clock running 1.4 µA
Normal mode supply current External 32-kHz clock running, charge pump and current source outputs disabled 0.6 mA
Charge pump in 1× mode, no load, current source outputs disabled 0.8 mA
Charge pump in 1.5× mode, no load, current source outputs disabled 1.8 mA
Power-save mode supply current External 32-kHz clock running 10 µA
Internal oscillator running 0.6 mA
ƒOSC Internal oscillator frequency accuracy –4% 4%
–7% 7%
(1) The Electrical Characteristics tables list ensured specifications under Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) All voltages are with respect to the potential at the GND pin.
(3) Minimum and maximum limits are ensured by design, test, or statistical analysis.
(4) Low-ESR surface-mount ceramic capacitors (MLCCs) used in setting electrical characteristics.

6.6 Charge Pump Electrical Characteristics

Unless otherwise noted: typical limits are for TA = 25°C; minimum and maximum limits apply over the operating ambient temperature range (−30°C < TA < +85°C). See(1)(2)(3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ROUT Charge pump output resistance Gain = 1.5× 3.5 Ω
Gain = 1× 1
ƒSW Switching frequency 1.25 MHz
IGND Ground current Gain = 1.5× 1.2 mA
Gain = 1× 0.3
tON VOUT turnon time (4) VDD = 3.6 V, IOUT = 60 mA 100 µs
(1) The Electrical Characteristics tables list ensured specifications under Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) All voltages are with respect to the potential at the GND pin.
(3) Minimum and maximum limits are ensured by design, test, or statistical analysis.
(4) Turnon time is measured from the moment the charge pump is activated until the VOUT crosses 90% of its target value.

6.7 LED Driver Electrical Characteristics

Unless otherwise noted limits apply for TA = 25°C. See(1)(2)(3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ILEAKAGE Leakage current (outputs D1 to D9) PWM = 0% 0.1 1 µA
IMAX Maximum source current Outputs D1 to D9 25.5 mA
IOUT Output current accuracy (4) Output current set to 17.5 mA −4% 4%
−30°C < TA < +85°C –5% 5%
IMATCH Matching (4) Output current set to 17.5 mA 1% 2.5%
ƒLED LED switching frequency 312 Hz
VSAT Saturation voltage (5) Output current set to 17.5 mA 45 100 mV
(1) The Electrical Characteristics tables list ensured specifications under Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) All voltages are with respect to the potential at the GND pin.
(3) Minimum and maximum limits are ensured by design, test, or statistical analysis.
(4) Output current accuracy is the difference between the actual value of the output current and programmed value of this current. Matching is the maximum difference from the average. For the constant current outputs on the part (D1 to D9), the following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Two matching numbers are calculated: (MAX – AVG) / AVG and (AVG – MIN) / AVG. The largest number of the two (worst case) is considered the matching figure. Note that some manufacturers have different definitions in use.
(5) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at VOUT – 1 V.

6.8 LED Test Electrical Characteristics

Unless otherwise noted limits apply for TA = 25°C. See(1)(2)(3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LSB Least significant bit 30 mV
EABS Total unadjusted error(4) VIN_TEST = 0 V to VDD < ±3 ±4 LSB
tCONV Conversion time 2.7 ms
VIN_TEST DC voltage range 0 5 V
(1) The Electrical Characteristics tables list ensured specifications under Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) All voltages are with respect to the potential at the GND pin.
(3) Minimum and maximum limits are ensured by design, test, or statistical analysis.
(4) Total unadjusted error includes offset, full-scale, and linearity errors.

6.9 Logic Interface Characteristics

Unless otherwise noted: typical limits are for TA = 25°C; minimum and maximum limits apply over the operating ambient temperature range (−30°C < TA < +85°C).See(1)(2)(3)(4)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC INPUT EN
VIL Input low level 0.5 V
VIH Input high level 1.2 V
II Input current −1 1 µA
tDELAY Input delay(4) 2 µs
LOGIC INPUT SCL, SDA, TRIG, CLK, ASEL0, ASEL1
VIL Input low level 0.2 × VEN V
VIH Input high level 0.8 × VEN V
II Input current −1 1 µA
LOGIC OUTPUT SDA, TRIG, INT
VOL Output low level IOUT = 3 mA (pullup current) 0.3 0.5 V
IL Output leakage current VOUT = 2.8 V 1 µA
LOGIC OUTPUT GPO
VOL Output low level IOUT = 3 mA 0.3 0.5 V
VOH Output high level IOUT = −2 mA VDD − 0.5 VDD − 0.3
IL Output leakage current VOUT = 2.8 V 1 µA
(1) The Electrical Characteristics tables list ensured specifications under Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) All voltages are with respect to the potential at the GND pin.
(3) Minimum and maximum limits are ensured by design, test, or statistical analysis.
(4) The I2C host must allow at least 500 µs before sending data to the LP5523 after the rising edge of the enable line.

6.10 Recommended External Clock Source Conditions

Unless otherwise noted limits apply for TA = 25°C. See(1)(2)(3) (4)(5)
MIN NOM MAX UNIT
LOGIC INPUT CLK
ƒCLK Clock frequency 32.7 kHz
tCLKH High time 6 µs
tCLKL Low time 6 µs
tr Clock rise time, 10% to 90% 2 µs
tf Clock fall time, 90% to 10% 2 µs
(1) The Electrical Characteristics tables list ensured specifications under Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) All voltages are with respect to the potential at the GND pin.
(3) Minimum and maximum limits are ensured by design, test, or statistical analysis.
(4) Specification is ensured by design and is not tested in production. VEN = 1.65 V to VDD.
(5) The ideal external clock signal for the LP5523 is a 0 V to VEN 25% to 75% duty-cycle square wave. At frequencies above 32.7 kHz, program execution is faster, and at frequencies below 32.7 kHz program execution is slower.

6.11 Serial Bus Timing Parameters (SDA, SCL)

Unless otherwise noted limits apply for TA = 25°C. See(1)(2)(3) (2)(3)
MIN MAX UNIT
fSCL Clock frequency 400 kHz
1 Hold time (repeated) START condition 0.6 µs
2 Clock low time 1.3 µs
3 Clock high time 600 ns
4 Setup TIME FOR A REPEATED START condition 600 ns
5 Data hold time 50 ns
6 Data setup time 100 ns
7 Rise time of SDA and SCL 20+0.1 Cb 300 ns
8 Fall time of SDA and SCL 15+0.1 Cb 300 ns
9 Set-up time for STOP condition 600 ns
10 Bus free time between a STOP and a START condition 1.3 µs
Cb Capacitive load parameter for each bus line.
Load of one picofarad corresponds to one nanosecond.		 10 200 ns
(1) The Electrical Characteristics tables list ensured specifications under Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) Minimum and maximum limits are ensured by design, test, or statistical analysis.
(3) Specification is ensured by design and is not tested in production. VEN = 1.65 V to VDD.
LP5523 300436300.png Figure 1. External Clock Signals
LP5523 30043600.png Figure 2. Serial Bus Timing Diagram

6.12 Typical Characteristics

Unless otherwise specified: VDD = 3.6 V, CIN = COUT = 1 µF, C1 = C2 = 0.47 µF, TA = 25°C; CIN, COUT, C1, C2: low-ESR surface-mount ceramic capacitors (MLCCs) used in setting electrical characteristics.
LP5523 300436301.png
Figure 3. Charge Pump 1.5× Efficiency vs Load Current
LP5523 300436305.png
6 × 1-mA Load 6 Nichia NSCW100 WLEDs on D1 To D6
Figure 5. Gain Change Hysteresis Loop At Factory Settings
LP5523 300436306.png
17.5-mA Current
See note 4 in LED Driver Electrical Characteristics
Figure 7. LED Current Matching Distribution
LP5523 30043677.gif
Charge Pump In 1× Mode
If the charge pump is OFF the supply current is even lower.
Figure 9. Power-Save Mode Supply Current vs VDD
LP5523 30043649.gif
Figure 11. 100% PWM RGB LED Efficiency vs VDD
LP5523 300436303.png
Figure 4. Charge Pump Output Voltage (1.5×) as a Function of Load Current at Four Input Voltage Levels
LP5523 300436302.png
Load = 6 × Nichia NSCW100 WLEDs on D1 To D6 at 100% PWM
Figure 6. Effect of Adaptive Hysteresis on the Width of the Hysteresis Loop
LP5523 300436304.png
17.5-mA Current
See note 4 in LED Driver Electrical Characteristics
Figure 8. LED Current Accuracy Distribution
LP5523 30043679.gif
VDD = 3.6 V ILOAD = 60 mA
Figure 10. Serial Bus Write (51h To Addr 36h) and
Charge-Pump Start-up Waveform
LP5523 30043650.gif
Figure 12. 100% PWM WLED Efficiency vs VDD