SLAS272H July   2000  – May 2018 MSP430F133 , MSP430F135 , MSP430F147 , MSP430F1471 , MSP430F148 , MSP430F1481 , MSP430F149 , MSP430F1491

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions for MSP430F13x and MSP430F14x
      2. Table 4-2 Signal Descriptions for MSP430F14x1
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Supply Current Into AVCC and DVCC Excluding External Current
    5. 5.5  Thermal Resistance Characteristics
    6. 5.6  Schmitt-Trigger Inputs – Ports P1, P2, P3, P4, P5, and P6
    7. 5.7  Standard Inputs – RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
    8. 5.8  Inputs – Px.y, TAx, TBx
    9. 5.9  Leakage Current
    10. 5.10 Outputs – Ports P1, P2, P3, P4, P5, and P6
    11. 5.11 Output Frequency
    12. 5.12 Typical Characteristics – Ports P1, P2, P3, P4, P5, and P6 Outputs
    13. 5.13 Wake-up Time From LPM3
    14. 5.14 RAM
    15. 5.15 Comparator_A
    16. 5.16 Typical Characteristics – Comparator_A
    17. 5.17 PUC and POR
    18. 5.18 DCO Frequency
    19. 5.19 DCO When Using ROSC
    20. 5.20 Crystal Oscillator, LFXT1
    21. 5.21 Crystal Oscillator, XT2
    22. 5.22 USART0, USART1
    23. 5.23 12-Bit ADC, Power Supply and Input Range Conditions
    24. 5.24 12-Bit ADC, External Reference
    25. 5.25 12-Bit ADC, Built-In Reference
    26. 5.26 12-Bit ADC, Timing Parameters
    27. 5.27 12-Bit ADC, Linearity Parameters
    28. 5.28 12-Bit ADC, Temperature Sensor and Built-In VMID
    29. 5.29 Flash Memory
    30. 5.30 JTAG Interface
    31. 5.31 JTAG Fuse
  6. 6Detailed Description
    1. 6.1 CPU
    2. 6.2 Instruction set
    3. 6.3 Operating Modes
    4. 6.4 Interrupt Vector Addresses
    5. 6.5 Bootloader (BSL)
    6. 6.6 JTAG Fuse Check Mode
    7. 6.7 Memory
      1. 6.7.1 Flash Memory
      2. 6.7.2 Special Function Registers
        1. Table 6-6   Interrupt Enable 1 Register Field Descriptions
        2. Table 6-7   Interrupt Enable 2 Register Field Descriptions
        3. Table 6-8   Interrupt Flag 1 Register Field Descriptions
        4. Table 6-9   Interrupt Flag 2 Register Field Descriptions
        5. Table 6-10 Module Enable 1 Bit Register Field Descriptions
        6. Table 6-11 Module Enable 2 Bit Register Field Descriptions
    8. 6.8 Peripherals
      1. 6.8.1  Digital I/O
      2. 6.8.2  Oscillator and System Clock
      3. 6.8.3  Watchdog Timer (WDT)
      4. 6.8.4  Hardware Multiplier (MSP430F14x and MSP430F14x1 Only)
      5. 6.8.5  USART0
      6. 6.8.6  USART1 (MSP430F14x and MSP430F14x1 Only)
      7. 6.8.7  Comparator_A
      8. 6.8.8  ADC12 (MSP430F14x and MSP430F13x Only)
      9. 6.8.9  Timer_A3
      10. 6.8.10 Timer_B3 (MSP430F13x Only)
      11. 6.8.11 Timer_B7 (MSP430F14x and MSP430F14x1 Only)
      12. 6.8.12 Peripheral File Map
    9. 6.9 Input/Output Diagrams
      1. 6.9.1 Port P1, Input/Output With Schmitt Trigger
      2. 6.9.2 Port P2, Input/Output With Schmitt Trigger
      3. 6.9.3 Port P3, Input/Output With Schmitt Trigger
      4. 6.9.4 Port P4, Input/Output With Schmitt Trigger
      5. 6.9.5 Port P5, Input/Output With Schmitt Trigger
      6. 6.9.6 Port P6, Input/Output With Schmitt Trigger
      7. 6.9.7 Port JTAG (TMS, TCK, TDI/TCLK, TDO/TDI), Input/Output With Schmitt Trigger
  7. 7Device and Documentation Support
    1. 7.1  Getting Started and Next Steps
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.2 Signal Descriptions

Table 4-1 describes the signals for the MSP430F13x and MSP430F14x MCUs. See Table 4-2 for the MSP430F14x1 signal descriptions.

Table 4-1 Signal Descriptions for MSP430F13x and MSP430F14x

SIGNAL NAME PIN NO. I/O DESCRIPTION
AVCC 64 Analog supply voltage, positive terminal. Supplies the analog portion of the ADC.
AVSS 62 Analog supply voltage, negative terminal. Supplies the analog portion of the ADC.
DVCC 1 Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS 63 Digital supply voltage, negative terminal. Supplies all digital parts.
P1.0/TACLK 12 I/O General-purpose digital I/O pin
Timer_A, clock signal TACLK input
P1.1/TA0 13 I/O General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output
BSL transmit
P1.2/TA1 14 I/O General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output
BSL transmit
P1.3/TA2 15 I/O General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK 16 I/O General-purpose digital I/O pin
SMCLK signal output
P1.5/TA0 17 I/O General-purpose digital I/O pin
Timer_A, compare: Out0 output
P1.6/TA1 18 I/O General-purpose digital I/O pin
Timer_A, compare: Out1 output
P1.7/TA2 19 I/O General-purpose digital I/O pin
Timer_A, compare: Out2 output/
P2.0/ACLK 20 I/O General-purpose digital I/O pin
ACLK output
P2.1/TAINCLK 21 I/O General-purpose digital I/O pin
Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0 22 I/O General-purpose digital I/O pin
Comparator_A output
Timer_A, capture: CCI0B input
BSL receive
P2.3/CA0/TA1 23 I/O General-purpose digital I/O pin
Timer_A, compare: Out1 output
Comparator_A input
P2.4/CA1/TA2 24 I/O General-purpose digital I/O pin
Timer_A, compare: Out2 output
Comparator_A input
P2.5/ROSC 25 I/O General-purpose digital I/O pin
input for external resistor defining the DCO nominal frequency
P2.6/ADC12CLK 26 I/O General-purpose digital I/O pin
Conversion clock for ADC
P2.7/TA0 27 I/O General-purpose digital I/O pin
Timer_A, compare: Out0 output
P3.0/STE0 28 I/O General-purpose digital I/O pin
Slave transmit enable for USART0 in SPI mode
P3.1/SIMO0 29 I/O General-purpose digital I/O pin
Slave in/master out of USART0 in SPI mode
P3.2/SOMI0 30 I/O General-purpose digital I/O pin
Slave out/master in of USART0 in SPI mode
P3.3/UCLK0 31 I/O General-purpose digital I/O
USART0 clock: external input in UART or SPI mode, output in SPI mode
P3.4/UTXD0 32 I/O General-purpose digital I/O pin
Transmit data out for USART0 in UART mode
P3.5/URXD0 33 I/O General-purpose digital I/O pin
Receive data in for USART0 in UART mode
P3.6/UTXD1(1) 34 I/O General-purpose digital I/O pin
Transmit data out for USART1 in UART mode
P3.7/URXD1(1) 35 I/O General-purpose digital I/O pin
Receive data in for USART1 in UART mode
P4.0/TB0 .36 I/O General-purpose digital I/O pin
Timer_B, capture: CCI0A or CCI0B input, compare: Out0 output
P4.1/TB1 37 I/O General-purpose digital I/O pin
Timer_B, capture: CCI1A or CCI1B input, compare: Out1 output
P4.2/TB2 38 I/O General-purpose digital I/O pin
Timer_B, capture: CCI2A or CCI2B input, compare: Out2 output
P4.3/TB3(1) 39 I/O General-purpose digital I/O pin
Timer_B, capture: CCI3A or CCI3B input, compare: Out3 output
P4.4/TB4(1) 40 I/O General-purpose digital I/O pin
Timer_B, capture: CCI4A or CCI4B input, compare: Out4 output
P4.5/TB5(1) 41 I/O General-purpose digital I/O pin
Timer_B, capture: CCI5A or CCI5B input, compare: Out5 output
P4.6/TB6(1) 42 I/O General-purpose digital I/O pin
Timer_B, capture: CCI6A or CCI6B input, compare: Out6 output
P4.7/TBCLK 43 I/O General-purpose digital I/O pin
Timer_B, clock signal TBCLK input
P5.0/STE1(1) 44 I/O General-purpose digital I/O pin
Slave transmit enable for USART1 in SPI mode
P5.1/SIMO1(1) 45 I/O General-purpose digital I/O pin
Slave in/master out of USART1 in SPI mode
P5.2/SOMI1(1) 46 I/O General-purpose digital I/O pin
Slave out/master in of USART1 in SPI mode
P5.3/UCLK1(1) 47 I/O General-purpose digital I/O pin
USART1 clock: external input in UART or SPI mode, output in SPI mode
P5.4/MCLK 48 I/O General-purpose digital I/O pin
Main system clock MCLK output
P5.5/SMCLK 49 I/O General-purpose digital I/O pin
Submain system clock SMCLK output
P5.6/ACLK 50 I/O General-purpose digital I/O pin
Auxiliary clock ACLK output
P5.7/TBOUTH 51 I/O General-purpose digital I/O pin
Switch all PWM digital output ports to high impedance for Timer_B7 (TB0 to TB6)
P6.0/A0 59 I/O General-purpose digital I/O pin
Analog input A0 for ADC
P6.1/A1 60 I/O General-purpose digital I/O pin
Analog input A1 for ADC
P6.2/A2 61 I/O General-purpose digital I/O pin
Analog input A2 for ADC
P6.3/A3 2 I/O General-purpose digital I/O pin
Analog input A3 for ADC
P6.4/A4 3 I/O General-purpose digital I/O pin
Analog input A4 for ADC
P6.5/A5 4 I/O General-purpose digital I/O pin
Analog input A5 for ADC
P6.6/A6 5 I/O General-purpose digital I/O pin
Analog input A6 for ADC
P6.7/A7 6 I/O General-purpose digital I/O pin
Analog input A7 for ADC
RST/NMI 58 I Reset input
Nonmaskable interrupt input port
Bootloader start
TCK 57 I Test clock, the clock input port for device programming test and bootloader start
TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDO/TDI 54 I/O Test data output or programming data input
TMS 56 I Test mode select, used as an input port for device programming and test
VeREF+ 10 I Input for an external reference voltage to the ADC
VREF+ 7 O Output of positive terminal of the reference voltage in the ADC
VREF−/VeREF− 11 I Negative terminal for the ADC reference voltage for both sources, the internal reference voltage or an external applied reference voltage
XIN 8 I Input port for crystal oscillator XT1, standard or watch crystals can be connected
XOUT 9 O Output terminal of crystal oscillator XT1
XT2IN 53 I Input port for crystal oscillator XT2, only standard crystals can be connected
XT2OUT 52 O Output terminal of crystal oscillator XT2
QFN Pad NA NA QFN package pad, connect to DVSS
(1) MSP430F14x devices only

Table 4-2 describes the signals for the MSP430F14x1 MCUs. See Table 4-1 for the MSP430F13x and MSP430F14x signal descriptions.

Table 4-2 Signal Descriptions for MSP430F14x1

SIGNAL NAME PIN NO. I/O DESCRIPTION
AVCC 64 Analog supply voltage positive terminal
AVSS 62 Analog supply voltage negative terminal
DVCC 1 Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS 63 Digital supply voltage, negative terminal. Supplies all digital parts.
P1.0/TACLK 12 I/O General-purpose digital I/O pin
Timer_A, clock signal TACLK input
P1.1/TA0 13 I/O General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output
BSL transmit
P1.2/TA1 14 I/O General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2 15 I/O General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK 16 I/O General-purpose digital I/O pin
SMCLK signal output
P1.5/TA0 17 I/O General-purpose digital I/O pin
Timer_A, compare: Out0 output
P1.6/TA1 18 I/O General-purpose digital I/O pin
Timer_A, compare: Out1 output
P1.7/TA2 19 I/O General-purpose digital I/O pin
Timer_A, compare: Out2 output
P2.0/ACLK 20 I/O General-purpose digital I/O pin
ACLK output
P2.1/TAINCLK 21 I/O General-purpose digital I/O pin
Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0 22 I/O General-purpose digital I/O pin
Timer_A, capture: CCI0B input
Comparator_A output
BSL receive
P2.3/CA0/TA1 23 I/O General-purpose digital I/O pin
Timer_A, compare: Out1 output
Comparator_A input
P2.4/CA1/TA2 24 I/O General-purpose digital I/O pin
Timer_A, compare: Out2 output
Comparator_A input
P2.5/ROSC 25 I/O General-purpose digital I/O pin
Input for external resistor defining the DCO nominal frequency
P2.6 26 I/O General-purpose digital I/O pin
P2.7/TA0 27 I/O General-purpose digital I/O pin
Timer_A, compare: Out0 output
P3.0/STE0 28 I/O General-purpose digital I/O pin
Slave transmit enable for USART0 in SPI mode
P3.1/SIMO0 29 I/O General-purpose digital I/O pin
Slave in/master out of USART0 in SPI mode
P3.2/SOMI0 30 I/O General-purpose digital I/O pin
Slave out/master in of USART0 in SPI mode
P3.3/UCLK0 31 I/O General-purpose digital I/O
USART0 clock: external input in UART or SPI mode, output in SPI mode
P3.4/UTXD0 32 I/O General-purpose digital I/O pin
Transmit data out for USART0 in UART mode
P3.5/URXD0 33 I/O General-purpose digital I/O pin
Receive data in for USART0 in UART mode
P3.6/UTXD1 34 I/O General-purpose digital I/O pin
Transmit data out for USART1 in UART mode
P3.7/URXD1 35 I/O General-purpose digital I/O pin
Receive data in for USART1 in UART mode
P4.0/TB0 .36 I/O General-purpose digital I/O pin
Timer_B, capture: CCI0A or CCI0B input, compare: Out0 output
P4.1/TB1 37 I/O General-purpose digital I/O pin
Timer_B, capture: CCI1A or CCI1B input, compare: Out1 output
P4.2/TB2 38 I/O General-purpose digital I/O pin
Timer_B, capture: CCI2A or CCI2B input, compare: Out2 output
P4.3/TB3 39 I/O General-purpose digital I/O pin
Timer_B, capture: CCI3A or CCI3B input, compare: Out3 output
P4.4/TB4 40 I/O General-purpose digital I/O pin
Timer_B, capture: CCI4A or CCI4B input, compare: Out4 output
P4.5/TB5 41 I/O General-purpose digital I/O pin
Timer_B, capture: CCI5A or CCI5B input, compare: Out5 output
P4.6/TB6 42 I/O General-purpose digital I/O pin
Timer_B, capture: CCI6A or CCI6B input, compare: Out6 output
P4.7/TBCLK 43 I/O General-purpose digital I/O pin
Timer_B, clock signal TBCLK input
P5.0/STE1 44 I/O General-purpose digital I/O pin
Slave transmit enable for USART1 in SPI mode
P5.1/SIMO1 45 I/O General-purpose digital I/O pin
Slave in/master out of USART1 in SPI mode
P5.2/SOMI1 46 I/O General-purpose digital I/O pin
Slave out/master in of USART1 in SPI mode
P5.3/UCLK1 47 I/O General-purpose digital I/O pin
USART1 clock: external input in UART or SPI mode, output in SPI mode
P5.4/MCLK 48 I/O General-purpose digital I/O pin
Main system clock MCLK output
P5.5/SMCLK 49 I/O General-purpose digital I/O pin
Submain system clock SMCLK output
P5.6/ACLK 50 I/O General-purpose digital I/O pin
Auxiliary clock ACLK output
P5.7/TBOUTH 51 I/O General-purpose digital I/O pin
Switch all PWM digital output ports to high impedance for Timer_B7 (TB0 to TB6)
P6.0 59 I/O General-purpose digital I/O pin
P6.1 60 I/O General-purpose digital I/O pin
P6.2 61 I/O General-purpose digital I/O pin
P6.3 2 I/O General-purpose digital I/O pin
P6.4 3 I/O General-purpose digital I/O pin
P6.5 4 I/O General-purpose digital I/O pin
P6.6 5 I/O General-purpose digital I/O pin
P6.7 6 I/O General-purpose digital I/O pin
RST/NMI 58 I Reset input
Nonmaskable interrupt input port
Bootloader start
TCK 57 I Test clock, the clock input port for device programming test and bootloader start
TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDO/TDI 54 I/O Test data output or programming data input
TMS 56 I Test mode select, used as an input port for device programming and test
DVSS 10 I Connect to DVSS
Reserved 7 Reserved, do not connect externally
DVSS 11 I Connect to DVSS
XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 O Output terminal of crystal oscillator XT1
XT2IN 53 I Input port for crystal oscillator XT2. Only standard crystals can be connected.
XT2OUT 52 O Output terminal of crystal oscillator XT2
QFN Pad NA NA QFN package pad, connect to DVSS