SLAS619R August   2010  – September 2018 MSP430F5131 , MSP430F5132 , MSP430F5151 , MSP430F5152 , MSP430F5171 , MSP430F5172

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.5, P3.2 to P3.7, and PJ.0 to PJ.6)
    8. 5.8  Schmitt-Trigger Inputs – General-Purpose I/O (P1.6 and P1.7, P2.0 to P2.7, and P3.0 and P3.1)
    9. 5.9  Inputs – Ports P1 and P2
    10. 5.10 Leakage Current – General-Purpose I/O
    11. 5.11 Outputs – Ports P1, P3, PJ (Full Drive Strength, P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6)
    12. 5.12 Outputs – Ports P1 to P3 (Full Drive Strength, P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1)
    13. 5.13 Outputs – Ports P1, P3, PJ (Reduced Drive Strength, P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6)
    14. 5.14 Outputs – Ports P1 to P3 (Reduced Drive Strength, P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1)
    15. 5.15 Output Frequency – Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    16. 5.16 Output Frequency – Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    17. 5.17 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    18. 5.18 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    19. 5.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    20. 5.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    21. 5.21 Crystal Oscillator, XT1, Low-Frequency Mode
    22. 5.22 Crystal Oscillator, XT1, High-Frequency Mode
    23. 5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    24. 5.24 Internal Reference, Low-Frequency Oscillator (REFO)
    25. 5.25 DCO Frequency
    26. 5.26 PMM, Brownout Reset (BOR)
    27. 5.27 PMM, Core Voltage
    28. 5.28 PMM, SVS High Side
    29. 5.29 PMM, SVM High Side
    30. 5.30 PMM, SVS Low Side
    31. 5.31 PMM, SVM Low Side
    32. 5.32 Wake-up Times From Low-Power Modes
    33. 5.33 Timer_A
    34. 5.34 USCI (UART Mode)
    35. 5.35 USCI (SPI Master Mode)
    36. 5.36 USCI (SPI Slave Mode)
    37. 5.37 USCI (I2C Mode)
    38. 5.38 10-Bit ADC, Power Supply and Input Range Conditions (MSP430F51x2 Devices Only)
    39. 5.39 10-Bit ADC, Timing Parameters (MSP430F51x2 Devices Only)
    40. 5.40 10-Bit ADC, Linearity Parameters (MSP430F51x2 Devices Only)
    41. 5.41 REF, External Reference (MSP430F51x2 Devices Only)
    42. 5.42 REF, Built-In Reference (MSP430F51x2 Devices Only)
    43. 5.43 Comparator_B
    44. 5.44 Timer_D, Power Supply and Reference Clock
    45. 5.45 Timer_D, Local Clock Generator Frequency
    46. 5.46 Timer_D, Trimmed Clock Frequencies
    47. 5.47 Timer_D, Frequency Multiplication Mode
    48. 5.48 Timer_D, Input Capture and Output Compare Timing
    49. 5.49 Flash Memory
    50. 5.50 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  Flash Memory
    8. 6.8  RAM
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O
      2. 6.9.2  Port Mapping Controller
      3. 6.9.3  Oscillator and System Clock
      4. 6.9.4  Power-Management Module (PMM)
      5. 6.9.5  Hardware Multiplier
      6. 6.9.6  Watchdog Timer (WDT_A)
      7. 6.9.7  System Module (SYS)
      8. 6.9.8  DMA Controller
      9. 6.9.9  Universal Serial Communication Interface (USCI)
      10. 6.9.10 TA0
      11. 6.9.11 TD0
      12. 6.9.12 TD1
      13. 6.9.13 Comparator_B
      14. 6.9.14 ADC10_A (MSP430F51x2 Only)
      15. 6.9.15 CRC16
      16. 6.9.16 Reference (REF) Module Voltage Reference
      17. 6.9.17 Embedded Emulation Module (EEM) (S Version)
      18. 6.9.18 Peripheral File Map
    10. 6.10 Input/Output Diagrams
      1. 6.10.1  Port P1 (P1.0 to P1.5) Input/Output With Schmitt Trigger
      2. 6.10.2  Port P1 (P1.6 to P1.7) Input/Output With Schmitt Trigger
      3. 6.10.3  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      4. 6.10.4  Port P3 (P3.0 and P3.1) Input/Output With Schmitt Trigger
      5. 6.10.5  Port P3 (P3.2 and P3.3) Input/Output With Schmitt Trigger
      6. 6.10.6  Port P3 (P3.4) Input/Output With Schmitt Trigger
      7. 6.10.7  Port P3 (P3.5) Input/Output With Schmitt Trigger
      8. 6.10.8  Port P3 (P3.6) Input/Output With Schmitt Trigger
      9. 6.10.9  Port P3 (P3.7) Input/Output With Schmitt Trigger
      10. 6.10.10 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      11. 6.10.11 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
      12. 6.10.12 Port J (PJ.4) Input/Output With Schmitt Trigger
      13. 6.10.13 Port J (PJ.5) Input/Output With Schmitt Trigger
      14. 6.10.14 Port J (PJ.6) Input/Output With Schmitt Trigger
    11. 6.11 Device Descriptors
  7. 7Device and Documentation Support
    1. 7.1  Getting Started and Next Steps
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.45 Timer_D, Local Clock Generator Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fHRCG(0,0,64) HRCG frequency (0, 0, 64) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1, TDHCLKRx = 0, TDHCLKSRx = 0, TDHCLKTRIM = 64 39 56 73 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1, TDHCLKRx = 0, TDHCLKSRx = 0, TDHCLKTRIM = 64 78 112 146
fHRCG(0,7,64) HRCG frequency (0, 7, 64) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1, TDHCLKRx = 0, TDHCLKSRx = 7, TDHCLKTRIM = 64 46 66 86 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1, TDHCLKRx = 0, TDHCLKSRx = 7, TDHCLKTRIM = 64 92 132 172
fHRCG(0,15,64) HRCG frequency (0, 15, 64) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1, TDHCLKRx = 0, TDHCLKSRx = 15, TDHCLKTRIM = 64 55 78 101 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1, TDHCLKRx = 0, TDHCLKSRx = 15, TDHCLKTRIM = 64 110 156 202
fHRCG(0,23,64) HRCG frequency (0, 23, 64) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1, TDHCLKRx = 0, TDHCLKSRx = 23, TDHCLKTRIM = 64 61 87 113 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1, TDHCLKRx = 0, TDHCLKSRx = 23, TDHCLKTRIM = 64 122 174 226
fHRCG(0,31,0) HRCG frequency (0, 31, 0) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1, TDHCLKRx = 0, TDHCLKSRx = 31, TDHCLKTRIM = 0 36 56 73 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1, TDHCLKRx = 0, TDHCLKSRx = 31, TDHCLKTRIM = 0 72 112 146
fHRCG(0,31,64) HRCG frequency (0, 31, 64) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1, TDHCLKRx = 0, TDHCLKSRx = 31, TDHCLKTRIM = 64 68 98 128 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1, TDHCLKRx = 0, TDHCLKSRx = 31, TDHCLKTRIM = 64 136 196 256
fHRCG(0,31,127) HRCG frequency (0, 31, 127) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1, TDHCLKRx = 0, TDHCLKSRx = 31, TDHCLKTRIM = 127 97 138 180 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1, TDHCLKRx = 0, TDHCLKSRx = 31, TDHCLKTRIM = 127 196 176 360
fHRCG(1,0,64) HRCG frequency (1, 0, 64) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 0, TDHCLKRx = 1, TDHCLKSRx = 0, TDHCLKTRIM = 64 71 101 131 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 0, TDHCLKRx = 1, TDHCLKSRx = 0, TDHCLKTRIM = 64 142 202 262
fHRCG(1,7,64) HRCG frequency (1, 7, 64) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 0, TDHCLKRx = 1, TDHCLKSRx = 7, TDHCLKTRIM = 64 84 120 156 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 0, TDHCLKRx = 1, TDHCLKSRx = 7, TDHCLKTRIM = 64 168 240 312
fHRCG(1,15,64) HRCG frequency (1, 15, 64) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 0, TDHCLKRx = 1, TDHCLKSRx = 15, TDHCLKTRIM = 64 97 139 182 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 0, TDHCLKRx = 1, TDHCLKSRx = 15, TDHCLKTRIM = 64 196 278 364
fHRCG(1,23,64) HRCG frequency (1, 23, 64) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 0, TDHCLKRx = 1, TDHCLKSRx = 23, TDHCLKTRIM = 64 108 154 200 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 0, TDHCLKRx = 1, TDHCLKSRx = 23, TDHCLKTRIM = 64 216 308 400
fHRCG(1,31,0) HRCG frequency (1, 31, 0) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 0, TDHCLKRx = 1, TDHCLKSRx = 31, TDHCLKTRIM = 0 68 97 126 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 0, TDHCLKRx = 1, TDHCLKSRx = 31, TDHCLKTRIM = 0 136 194 252
fHRCG(1,31,64) HRCG frequency (1, 31, 64) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 0, TDHCLKRx = 1, TDHCLKSRx = 31, TDHCLKTRIM = 64 123 175 227 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 0, TDHCLKRx = 1, TDHCLKSRx = 31, TDHCLKTRIM = 64 246 350 454
fHRCG(1,31,127) HRCG frequency (1, 31, 127) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 0, TDHCLKRx = 1, TDHCLKSRx = 31, TDHCLKTRIM = 127 169 241 313 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 0, TDHCLKRx = 1, TDHCLKSRx = 31, TDHCLKTRIM = 127 338 482 616
fHRCG(2,0,64) HRCG frequency (2, 0, 64) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1, TDHCLKRx = 2, TDHCLKSRx = 0, TDHCLKTRIM = 64 126 180 234 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1, TDHCLKRx = 1, TDHCLKSRx = 0, TDHCLKTRIM = 64 252 360 468
fHRCG(2,7,64) HRCG frequency (2, 7, 64) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1, TDHCLKRx = 2, TDHCLKSRx = 7, TDHCLKTRIM = 64 138 208 270 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1, TDHCLKRx = 2, TDHCLKSRx = 7, TDHCLKTRIM = 6 276 416 540
fHRCG(2,15,64) HRCG frequency (2, 15, 64) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1, TDHCLKRx = 2, TDHCLKSRx = 15, TDHCLKTRIM = 64 168 240 312 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1, TDHCLKRx = 2, TDHCLKSRx = 15, TDHCLKTRIM = 64 336 480 624
fHRCG(2,23,64) HRCG frequency (2, 23, 64) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1, TDHCLKRx = 2, TDHCLKSRx = 23, TDHCLKTRIM = 64 189 270 351 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1, TDHCLKRx = 2, TDHCLKSRx = 23, TDHCLKTRIM = 64 378 540 702
fHRCG(2,31,0) HRCG frequency (2, 31, 0) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1, TDHCLKRx = 2, TDHCLKSRx = 31, TDHCLKTRIM = 0 119 170 221 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1, TDHCLKRx = 2, TDHCLKSRx = 31, TDHCLKTRIM = 0 238 340 442
fHRCG(2,31,64) HRCG frequency (2, 31, 64) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1, TDHCLKRx = 2, DHCLKSRx = 31, TDHCLKTRIM = 64 212 303 394 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1, TDHCLKRx = 2, DHCLKSRx = 31, TDHCLKTRIM = 64 424 606 788
fHRCG(2,31,127) HRCG frequency (2, 31, 127) TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1, TDHCLKRx = 2, TDHCLKSRx = 31, TDHCLKTRIM = 127 290 413 537 MHz
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1, TDHCLKRx = 2, TDHCLKSRx = 31, TDHCLKTRIM = 127 580 826 1074
SHRCG,0,SR TDHCLKSRx step size in range 0 SHRCGSR = fHRCGSR(HRCGSR+1) – fHRCG(HRCGSR) 120 185 225 kHz
SHRCG,1,SR TDHCLKSRx step size in range 1 SHRCGSR = fHRCGSR(HRCGSR+1) – fHRCG(HRCGSR) 220 325 395 kHz
SHRCG,2,SR TDHCLKSRx step size in range 2 SHRCGSR = fHRCGSR(HRCGSR+1) – fHRCG(HRCGSR) 400 555 700 kHz
SHRCG,0,TRIM 0 > = TDHCLKTRIMx < 16,
step size in range 0		 SHRCGSR = fHRCGSR(HRCGTRIM+1) – fHRCG(HRCGTRIM), TDHCLKSRx = X, Y, Z 55 85 120 kHz
15 < TDHCLKTRIMx < 49,
step size in range 1		 40 85 130
48 < TDHCLKTRIMx < 64,
step size in range 2		 40 85 120
SHRCG,1,TRIM 0 > = TDHCLKTRIMx < 16,
step size in range 0		 SHRCGSR = fHRCGSR(HRCGTRIM+1) – fHRCG(HRCGTRIM), TDHCLKSRx = X, Y, Z 90 160 230 kHz
15 < TDHCLKTRIMx < 49,
step size in range 1		 80 160 230
48 < TDHCLKTRIMx < 64,
step size in range 2		 80 160 230
SHRCG,2,TRIM 0 > = TDHCLKTRIMx < 16,
step size in range 0		 SHRCGSR = fHRCGSR(HRCGTRIM+1) – fHRCG(HRCGTRIM), TDHCLKSRx = X, Y, Z 150 230 360 kHz
15 < TDHCLKTRIMx < 49,
step size in range 1		 130 230 350
48 < TDHCLKTRIMx < 32,
step size in range 2		 100 230 340
dfHRCG/dT HRCG frequency temperature drift fHRCG = 8 MHz, TDHREGEN = 0 ±0.17 %/°C
fHRCG = 16 MHz, TDHREGEN = 0 ±0.16
fHRCG = 25 MHz, TDHREGEN = 0 ±0.16
fHRCG = 8, 16, or 25 MHz, TDHREGEN = 1 0
dfHRCG/ dVDVCC HRCG frequency voltage drift fHRCG = 8, 16, or 25 MHz, TDHREGEN = 0 0 5 %/V
fHRCG = 8, 16, or 25 MHz, TDHREGEN = 1 0
tSETTLE Settling time TDHEN = 0 → 1, TDHFW = 0 3 5 9 µs
Settling time, fast wake-up TDHEN = 0 → 1, TDHFW = 1 1.5