SLAS897B September   2013  – September 2018 MSP430F5232 , MSP430F5234 , MSP430F5237 , MSP430F5239 , MSP430F5242 , MSP430F5244 , MSP430F5247 , MSP430F5249

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
      2. 4.2.1     RST/NMI and RSTDVCC/SBWTDIO Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, P7.0 to P7.5, PJ.0 to PJ.3, RSTDVCC/SBWTDIO, RST/NMI)
    8. 5.8  Inputs – Interrupts (P1.0 to P1.7, P2.0 to P2.7)
    9. 5.9  Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, P7.0 to P7.5, PJ.0 to PJ.3)
    10. 5.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, P7.0 to P7.5, PJ.0 to PJ.3)
    11. 5.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, P7.0 to P7.5, PJ.0 to PJ.3)
    12. 5.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, P7.0 to P7.5, PJ.0 to PJ.3)
    13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16 Crystal Oscillator, XT2
    17. 5.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 5.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 5.19 DCO Frequency
    20. 5.20 PMM, Brownout Reset (BOR)
    21. 5.21 PMM, Core Voltage
    22. 5.22 PMM, SVS High Side
    23. 5.23 PMM, SVM High Side
    24. 5.24 PMM, SVS Low Side
    25. 5.25 PMM, SVM Low Side
    26. 5.26 Wake-up Times From Low-Power Modes and Reset
    27. 5.27 Timer_A
    28. 5.28 Timer_B
    29. 5.29 USCI (UART Mode) Clock Frequency
    30. 5.30 USCI (UART Mode)
    31. 5.31 USCI (SPI Master Mode) Clock Frequency
    32. 5.32 USCI (SPI Master Mode)
    33. 5.33 USCI (SPI Slave Mode)
    34. 5.34 USCI (I2C Mode)
    35. 5.35 10-Bit ADC, Power Supply and Input Range Conditions
    36. 5.36 10-Bit ADC, Timing Parameters
    37. 5.37 10-Bit ADC, Linearity Parameters
    38. 5.38 REF, External Reference
    39. 5.39 REF, Built-In Reference
    40. 5.40 Comparator_B
    41. 5.41 Flash Memory
    42. 5.42 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU (Link to User's Guide)
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  Flash Memory (Link to User's Guide)
    8. 6.8  RAM (Link to User's Guide)
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O (Link to User's Guide)
      2. 6.9.2  Port Mapping Controller (Link to User's Guide)
      3. 6.9.3  Oscillator and System Clock (Link to User's Guide)
      4. 6.9.4  Power-Management Module (PMM) (Link to User's Guide)
      5. 6.9.5  Hardware Multiplier (MPY) (Link to User's Guide)
      6. 6.9.6  Real-Time Clock (RTC_A) (Link to User's Guide)
      7. 6.9.7  Watchdog Timer (WDT_A) (Link to User's Guide)
      8. 6.9.8  System (SYS) Module (Link to User's Guide)
      9. 6.9.9  DMA Controller (Link to User's Guide)
      10. 6.9.10 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      11. 6.9.11 TA0 (Link to User's Guide)
      12. 6.9.12 TA1 (Link to User's Guide)
      13. 6.9.13 TA2 (Link to User's Guide)
      14. 6.9.14 TB0 (Link to User's Guide)
      15. 6.9.15 Comparator_B (Link to User's Guide)
      16. 6.9.16 ADC10_A (Link to User's Guide)
      17. 6.9.17 CRC16 (Link to User's Guide)
      18. 6.9.18 Reference (REF) Module Voltage Reference (Link to User's Guide)
      19. 6.9.19 Embedded Emulation Module (EEM) (S Version) (Link to User's Guide)
      20. 6.9.20 Peripheral File Map
    10. 6.10 Input/Output Diagrams
      1. 6.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.10.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 6.10.3  Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
      4. 6.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 6.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 6.10.6  Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
      7. 6.10.7  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      8. 6.10.8  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      9. 6.10.9  Port P7 (P7.0 to P7.5) Input/Output With Schmitt Trigger
      10. 6.10.10 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      11. 6.10.11 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 6.11 Device Descriptors
  7. 7Device and Documentation Support
    1. 7.1  Getting Started and Next Steps
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Signal Descriptions

Table 4-1 describes the signals for all device variants and package options.

Table 4-1 Signal Descriptions

TERMINAL I/O(1) DESCRIPTION
NAME NO.
RGC ZQE RGZ
P6.4/CB4/A4 5 C1 2 I/O General-purpose digital I/O
Comparator_B input CB4
Analog input A4 for the ADC (not available on all device types)
P6.5/CB5/A5 6 D2 3 I/O General-purpose digital I/O
Comparator_B input CB5
Analog input A5 for the ADC (not available on all device types)
P6.6/CB6/A6 7 D1 N/A I/O General-purpose digital I/O (not available on all device types)
Comparator_B input CB6 (not available on all device types)
Analog input A6 for the ADC (not available on all device types)
P6.7/CB7/A7 8 D3 N/A I/O General-purpose digital I/O (not available on all device types)
Comparator_B input CB7 (not available on all device types)
Analog input A7 for the ADC (not available on all device types)
P5.0/A8/VeREF+ 9 E1 4 I/O General-purpose digital I/O
Analog input A8 for the ADC (not available on all device types)
Input for an external reference voltage to the ADC (not available on all device types)
P5.1/A9/VeREF- 10 E2 5 I/O General-purpose digital I/O
Analog input A9 for the ADC (not available on all device types)
Negative terminal for the ADC reference voltage for an external applied reference voltage (not available on all device types)
AVCC 11 F2 6 Analog power supply
P5.4/XIN 12 F1 7 I/O General-purpose digital I/O
Input terminal for crystal oscillator XT1
P5.5/XOUT 13 G1 8 I/O General-purpose digital I/O
Output terminal of crystal oscillator XT1
AVSS 14 G2 9 Analog ground supply
DVCC 15 H1 10 Digital power supply
DVSS 16 J1 11 Digital ground supply
VCORE(4) 17 J2 12 Regulated core power supply output (internal use only, no external current loading)
P1.0/TA0CLK/ACLK 18 H2 13 I/O General-purpose digital I/O with port interrupt
TA0 clock signal TA0CLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P1.1/TA0.0 19 H3 14 I/O General-purpose digital I/O with port interrupt
TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
P1.2/TA0.1 20 J3 15 I/O General-purpose digital I/O with port interrupt
TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
P1.3/TA0.2 21 G4 16 I/O General-purpose digital I/O with port interrupt
TA0 CCR2 capture: CCI2A input, compare: Out2 output
P1.4/TA0.3 22 H4 17 I/O General-purpose digital I/O with port interrupt
TA0 CCR3 capture: CCI3A input compare: Out3 output
P1.5/TA0.4 23 J4 18 I/O General-purpose digital I/O with port interrupt
TA0 CCR4 capture: CCI4A input, compare: Out4 output
P1.6/TA1CLK/CBOUT 24 G5 19 I/O General-purpose digital I/O with port interrupt
TA1 clock signal TA1CLK input
Comparator_B output
P1.7/TA1.0 25 H5 20 I/O General-purpose digital I/O with port interrupt
TA1 CCR0 capture: CCI0A input, compare: Out0 output
P2.0/TA1.1 26 J5 N/A I/O General-purpose digital I/O with port interrupt (not available on all device types)
TA1 CCR1 capture: CCI1A input, compare: Out1 output (not available on all device types)
P2.1/TA1.2 27 G6 N/A I/O General-purpose digital I/O with port interrupt (not available on all device types)
TA1 CCR2 capture: CCI2A input, compare: Out2 output (not available on all device types)
P2.2/TA2CLK/SMCLK 28 J6 N/A I/O General-purpose digital I/O with port interrupt (not available on all device types)
TA2 clock signal TA2CLK input
SMCLK output (not available on all device types)
P2.3/TA2.0 29 H6 N/A I/O General-purpose digital I/O with port interrupt (not available on all device types)
TA2 CCR0 capture: CCI0A input, compare: Out0 output (not available on all device types)
P2.4/TA2.1 30 J7 N/A I/O General-purpose digital I/O with port interrupt (not available on all device types)
TA2 CCR1 capture: CCI1A input, compare: Out1 output (not available on all device types)
P2.5/TA2.2 31 J8 N/A I/O General-purpose digital I/O with port interrupt (not available on all device types)
TA2 CCR2 capture: CCI2A input, compare: Out2 output (not available on all device types)
P2.6/RTCCLK/DMAE0 32 J9 N/A I/O General-purpose digital I/O with port interrupt (not available on all device types)
RTC clock output for calibration (not available on all device types)
DMA external trigger input (not available on all device types)
P2.7/UCB0STE/UCA0CLK 33 H7 21 I/O General-purpose digital I/O
Slave transmit enable for USCI_B0 SPI mode
Clock signal input for USCI_A0 SPI slave mode
Clock signal output for USCI_A0 SPI master mode
P3.0/UCB0SIMO/UCB0SDA 34 H8 22 I/O General-purpose digital I/O
Slave in, master out for USCI_B0 SPI mode
I2C data for USCI_B0 I2C mode
P3.1/UCB0SOMI/UCB0SCL 35 H9 23 I/O General-purpose digital I/O
Slave out, master in for USCI_B0 SPI mode
I2C clock for USCI_B0 I2C mode
P3.2/UCB0CLK/UCA0STE 36 G8 24 I/O General-purpose digital I/O
Clock signal input for USCI_B0 SPI slave mode
Clock signal output for USCI_B0 SPI master mode
Slave transmit enable for USCI_A0 SPI mode
P3.3/UCA0TXD/UCA0SIMO 37 G9 25 I/O General-purpose digital I/O
Transmit data for USCI_A0 UART mode
Slave in, master out for USCI_A0 SPI mode
P3.4/UCA0RXD/UCA0SOMI 38 G7 26 I/O General-purpose digital I/O
Receive data for USCI_A0 UART mode
Slave out, master in for USCI_A0 SPI mode
DVSS 39 F9 27 Digital ground supply
DVCC 40 E9 28 Digital power supply
P4.0/PM_UCB1STE/ PM_UCA1CLK 41 E8 29 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave transmit enable for USCI_B1 SPI mode
Default mapping: Clock signal input for USCI_A1 SPI slave mode
Default mapping: Clock signal output for USCI_A1 SPI master mode
P4.1/PM_UCB1SIMO/ PM_UCB1SDA 42 E7 30 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave in, master out for USCI_B1 SPI mode
Default mapping: I2C data for USCI_B1 I2C mode
P4.2/PM_UCB1SOMI/ PM_UCB1SCL 43 D9 31 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave out, master in for USCI_B1 SPI mode
Default mapping: I2C clock for USCI_B1 I2C mode
P4.3/PM_UCB1CLK/ PM_UCA1STE 44 D8 32 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Clock signal input for USCI_B1 SPI slave mode
Default mapping: Clock signal output for USCI_B1 SPI master mode
Default mapping: Slave transmit enable for USCI_A1 SPI mode
P4.4/PM_UCA1TXD/ PM_UCA1SIMO 45 D7 33 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Transmit data for USCI_A1 UART mode
Default mapping: Slave in, master out for USCI_A1 SPI mode
P4.5/PM_UCA1RXD/ PM_UCA1SOMI 46 C9 34 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Receive data for USCI_A1 UART mode
Default mapping: Slave out, master in for USCI_A1 SPI mode
P4.6/PM_NONE 47 C8 35 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: no secondary function.
P4.7/PM_NONE 48 C7 N/A I/O General-purpose digital I/O with reconfigurable port mapping secondary function (not available on all device types)
Default mapping: no secondary function. (not available on all device types)
P7.0/TB0.0 49 B8, B9 N/A I/O General-purpose digital I/O (not available on all device types)
TB0 CCR0 capture: CCI0A input, compare: Out0 output (not available on all device types)
P7.1/TB0.1 50 A9 N/A I/O General-purpose digital I/O (not available on all device types)
TB0 CCR1 capture: CCI1A input, compare: Out1 output (not available on all device types)
P7.2/TB0.2 51 B7 N/A I/O General-purpose digital I/O (not available on all device types)
TB0 CCR2 capture: CCI2A input, compare: Out2 output (not available on all device types)
P7.3/TB0.3 52 A8 N/A I/O General-purpose digital I/O (not available on all device types)
TB0 CCR3 capture: CCI3A input, compare: Out3 output (not available on all device types)
P7.4/TB0.4 53 A7 N/A I/O General-purpose digital I/O (not available on all device types)
TB0 CCR4 capture: CCI4A input, compare: Out4 output (not available on all device types)
P7.5/TB0.5 54 A6 N/A I/O General-purpose digital I/O (not available on all device types)
TB0 CCR5 capture: CCI5A input, compare: Out5 output (not available on all device types)
RST/NMI 56 A5 37 I Reset input, active low (also see Section 4.2.1)(7)
Nonmaskable interrupt input
P5.2/XT2IN 57 B5 38 I/O General-purpose digital I/O
Input terminal for crystal oscillator XT2
P5.3/XT2OUT 58 B4 39 I/O General-purpose digital I/O \
Output terminal of crystal oscillator XT2
TEST/SBWTCK(5) 59 A4 40 I Test mode pin – Selects four-wire JTAG operation
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
PJ.0/TDO(6) 60 C5 41 I/O General-purpose digital I/O
JTAG test data output port
PJ.1/TDI/TCLK(6) 61 C4 42 I/O General-purpose digital I/O
JTAG test data input or test clock input
PJ.2/TMS(6) 62 A3 43 I/O General-purpose digital I/O
JTAG test mode select
PJ.3/TCK(6) 63 B3 44 I/O General-purpose digital I/O
JTAG test clock
RSTDVCC/SBWTDIO(6) 64 A2 45 I/O Reset input active low (also see Section 4.2.1)(8)
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated
P6.0/CB0/A0 1 A1 46 I/O General-purpose digital I/O
Comparator_B input CB0
Analog input A0 for the ADC (not available on all device types)
P6.1/CB1/A1 2 B2 47 I/O General-purpose digital I/O
Comparator_B input CB1
Analog input A1 for the ADC (not available on all device types)
P6.2/CB2/A2 3 B1 48 I/O General-purpose digital I/O
Comparator_B input CB2
Analog input A2 for the ADC (not available on all device types)
P6.3/CB3/A3 4 C2 1 I/O General-purpose digital I/O
Comparator_B input CB3
Analog input A3 for the ADC (not available on all device types)
Reserved 55(2)  (3) 36(2) Reserved
QFN Pad Pad N/A Pad QFN package pad. Connection to VSS recommended.
I = input, O = output, N/A = not available
This pin is reserved and can be left unconnected or connected to ground.
Pins C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground. Pin B6 is reserved and can be left unconnected or connected to ground.
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE.
See Section 6.5 and Section 6.6 for use with BSL and JTAG functions, respectively.
See Section 6.6 for use with JTAG function.
When this pin is configured as reset, the internal pullup resistor is enabled by default.
This nonconfigurable reset has an internal pullup to DVCC.