SLAS731D December   2011  – September 2018 MSP430F6720 , MSP430F6721 , MSP430F6723 , MSP430F6724 , MSP430F6725 , MSP430F6726 , MSP430F6730 , MSP430F6731 , MSP430F6733 , MSP430F6734 , MSP430F6735 , MSP430F6736

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-3 Terminal Functions, PZ Package
      2. Table 4-4 Terminal Functions, PN Package
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Thermal Resistance Characteristics
    8. 5.8  Digital I/O Ports
      1. Table 5-1 Schmitt-Trigger Inputs – General-Purpose I/O
      2. Table 5-2 Inputs – Ports P1 and P2
      3. Table 5-3 Leakage Current – General-Purpose I/O
      4. Table 5-4 Outputs – General-Purpose I/O (Full Drive Strength)
      5. Table 5-5 Typical Characteristics – General-Purpose I/O (Full Drive Strength)
      6. Table 5-6 Outputs – General-Purpose I/O (Reduced Drive Strength)
      7. 5.8.1     Typical Characteristics – General-Purpose I/O (Reduced Drive Strength)
      8. Table 5-7 Output Frequency – General-Purpose I/O
    9. 5.9  Clock Specifications
      1. Table 5-8  Crystal Oscillator, XT1, Low-Frequency Mode
      2. Table 5-9  Internal Very-Low-Power Low-Frequency Oscillator (VLO)
      3. Table 5-10 Internal Reference, Low-Frequency Oscillator (REFO)
      4. Table 5-11 DCO Frequency
    10. 5.10 Power-Management Module (PMM)
      1. Table 5-12 PMM, Brownout Reset (BOR)
      2. Table 5-13 PMM, Core Voltage
      3. Table 5-14 PMM, SVS High Side
      4. Table 5-15 PMM, SVM High Side
      5. Table 5-16 PMM, SVS Low Side
      6. Table 5-17 PMM, SVM Low Side
      7. Table 5-18 Wake-up Times From Low-Power Modes and Reset
    11. 5.11 Auxiliary Supplies
      1. Table 5-19 Auxiliary Supplies, Recommended Operating Conditions
      2. Table 5-20 Auxiliary Supplies, AUXVCC3 (Backup Subsystem) Currents
      3. Table 5-21 Auxiliary Supplies, Auxiliary Supply Monitor
      4. Table 5-22 Auxiliary Supplies, Switch ON-Resistance
      5. Table 5-23 Auxiliary Supplies, Switching Time
      6. Table 5-24 Auxiliary Supplies, Switch Leakage
      7. Table 5-25 Auxiliary Supplies, Auxiliary Supplies to ADC10_A
      8. Table 5-26 Auxiliary Supplies, Charge Limiting Resistor
    12. 5.12 Timer_A
      1. Table 5-27 Timer_A
    13. 5.13 eUSCI
      1. Table 5-28 eUSCI (UART Mode) Clock Frequency
      2. Table 5-29 eUSCI (UART Mode) Switching Characteristics
      3. Table 5-30 eUSCI (SPI Master Mode) Clock Frequency
      4. Table 5-31 eUSCI (SPI Master Mode) Switching Characteristics
      5. Table 5-32 eUSCI (SPI Slave Mode)
      6. Table 5-33 eUSCI (I2C Mode)
    14. 5.14 LCD Controller
      1. Table 5-34 LCD_C Recommended Operating Conditions
      2. Table 5-35 LCD_C Electrical Characteristics
    15. 5.15 SD24_B
      1. Table 5-36 SD24_B Power Supply and Recommended Operating Conditions
      2. Table 5-37 SD24_B Analog Input
      3. Table 5-38 SD24_B Supply Currents
      4. Table 5-39 SD24_B Performance
      5. Table 5-40 SD24_B AC Performance
      6. Table 5-41 SD24_B AC Performance
      7. Table 5-42 SD24_B AC Performance
      8. Table 5-43 SD24_B External Reference Input
    16. 5.16 ADC10_A
      1. Table 5-44 10-Bit ADC, Power Supply and Input Range Conditions
      2. Table 5-45 10-Bit ADC, Timing Parameters
      3. Table 5-46 10-Bit ADC, Linearity Parameters
      4. Table 5-47 10-Bit ADC, External Reference
    17. 5.17 REF
      1. Table 5-48 REF, Built-In Reference
    18. 5.18 Flash Memory
      1. Table 5-49 Flash Memory
    19. 5.19 Emulation and Debug
      1. Table 5-50 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  Flash Memory
    9. 6.9  RAM
    10. 6.10 Backup RAM
    11. 6.11 Peripherals
      1. 6.11.1  Oscillator and System Clock
      2. 6.11.2  Power Management Module (PMM)
      3. 6.11.3  Auxiliary Supply System
      4. 6.11.4  Backup Subsystem
      5. 6.11.5  Digital I/O
      6. 6.11.6  Port Mapping Controller
      7. 6.11.7  System Module (SYS)
      8. 6.11.8  Watchdog Timer (WDT_A)
      9. 6.11.9  DMA Controller
      10. 6.11.10 CRC16
      11. 6.11.11 Hardware Multiplier
      12. 6.11.12 Enhanced Universal Serial Communication Interface (eUSCI)
      13. 6.11.13 ADC10_A
      14. 6.11.14 SD24_B
      15. 6.11.15 TA0
      16. 6.11.16 TA1
      17. 6.11.17 TA2
      18. 6.11.18 TA3
      19. 6.11.19 SD24_B Triggers
      20. 6.11.20 ADC10_A Triggers
      21. 6.11.21 Real-Time Clock (RTC_C)
      22. 6.11.22 Reference (REF) Module Voltage Reference
      23. 6.11.23 LCD_C
      24. 6.11.24 Embedded Emulation Module (EEM) (S Version)
      25. 6.11.25 Peripheral File Map
    12. 6.12 Input/Output Diagrams
      1. 6.12.1  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger (MSP430F67xxIPZ and MSP430F67xxIPN)
      2. 6.12.2  Port P1 (P1.2) Input/Output With Schmitt Trigger (MSP430F67xxIPZ and MSP430F67xxIPN)
      3. 6.12.3  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger (MSP430F67xxIPZ and MSP430F67xxIPN)
      4. 6.12.4  Port P1 (P1.6 and P1.7) (MSP430F67xxIPZ and MSP430F67xxIPN), Port P2 (P2.0 and P2.1) (MSP430F67xxIPZ Only) Input/Output With Schmitt Trigger
      5. 6.12.5  Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      6. 6.12.6  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      7. 6.12.7  Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      8. 6.12.8  Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to P7.7), Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      9. 6.12.9  Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      10. 6.12.10 Port P9 (P9.0) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      11. 6.12.11 Port P9 (P9.1 to P9.3) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      12. 6.12.12 Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
      13. 6.12.13 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
      14. 6.12.14 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
      15. 6.12.15 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
      16. 6.12.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      17. 6.12.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    13. 6.13 Device Descriptors (TLV)
  7. 7Device and Documentation Support
    1. 7.1  Getting Started and Next Steps
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

TA0

TA0 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA0 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-13). TA0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 6-13 TA0 Signal Connections

DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
PM_TACLK TACLK Timer NA NA
ACLK (internal) ACLK
SMCLK (internal) SMCLK
PM_TACLK INCLK
PM_TA0.0 CCI0A CCR0 TA0 PM_TA0.0
DVSS CCI0B
DVSS GND
DVCC VCC
PM_TA0.1 CCI1A CCR1 TA1 PM_TA0.1
ACLK (internal) CCI1B ADC10_A (internal)
ADC10SHSx = \{1\}
DVSS GND SD24_B (internal)
SD24SCSx = \{1\}
DVCC VCC
PM_TA0.2 CCI2A CCR2 TA2 PM_TA0.2
DVSS CCI2B
DVSS GND
DVCC VCC