SLAS380D April   2004  – November 2014 MSP430FG437 , MSP430FG438 , MSP430FG439

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3 Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Handling Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Supply Current Into AVCC + DVCC Excluding External Current
    5. 5.5  Schmitt-Trigger Inputs - Ports P1 to P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
    6. 5.6  Inputs Px.y, TAx, TBx
    7. 5.7  Leakage Current - Ports P1 to P6
    8. 5.8  Outputs - Ports P1 to P6
    9. 5.9  Output Frequency
    10. 5.10 Typical Characteristics - Outputs
    11. 5.11 Wake-Up From LPM3
    12. 5.12 RAM
    13. 5.13 LCD
    14. 5.14 Comparator_A
    15. 5.15 Comparator_A Typical Characteristics
    16. 5.16 Power-On Reset (POR) and Brownout Reset (BOR)
    17. 5.17 Supply Voltage Supervisor (SVS) and Supply Voltage Monitor (SVM)
    18. 5.18 DCO
    19. 5.19 Crystal Oscillator, XT1 Oscillator
    20. 5.20 Crystal Oscillator, XT2 Oscillator
    21. 5.21 USART0
    22. 5.22 12-Bit ADC, Power Supply and Input Range Conditions
    23. 5.23 12-Bit ADC, External Reference
    24. 5.24 12-Bit ADC, Built-In Reference
    25. 5.25 12-Bit ADC, Timing Parameters
    26. 5.26 12-Bit ADC, Linearity Parameters
    27. 5.27 12-Bit ADC, Temperature Sensor and Built-In VMID
    28. 5.28 12-Bit DAC, Supply Specifications
    29. 5.29 12-Bit DAC, Linearity Specifications
    30. 5.30 12-Bit DAC, Output Specifications
    31. 5.31 12-Bit DAC, Reference Input Specifications
    32. 5.32 12-Bit DAC, Dynamic Specifications
    33. 5.33 12-Bit DAC, Dynamic Specifications (Continued)
    34. 5.34 Operational Amplifier (OA), Supply Specifications
    35. 5.35 Operational Amplifier (OA), Input/Output Specifications
    36. 5.36 Operational Amplifier (OA), Dynamic Specifications
    37. 5.37 OA Dynamic Specifications Typical Characteristics
    38. 5.38 Flash Memory
    39. 5.39 JTAG Interface
    40. 5.40 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers (SFRs)
      1. 6.5.1 Interrupt Enable Registers 1 and 2
      2. 6.5.2 Interrupt Flag Registers 1 and 2
      3. 6.5.3 Module Enable Registers 1 and 2
    6. 6.6  Memory Organization
    7. 6.7  Bootstrap Loader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
      1. 6.9.1  DMA Controller
      2. 6.9.2  Oscillator and System Clock
      3. 6.9.3  Brownout, Supply Voltage Supervisor
      4. 6.9.4  Digital I/O
      5. 6.9.5  Basic Timer1
      6. 6.9.6  LCD Drive
      7. 6.9.7  OA
      8. 6.9.8  Watchdog Timer (WDT)
      9. 6.9.9  USART0
      10. 6.9.10 Timer_A3
      11. 6.9.11 Timer_B3
      12. 6.9.12 Comparator_A
      13. 6.9.13 ADC12
      14. 6.9.14 DAC12
      15. 6.9.15 Peripheral File Map
    10. 6.10 Input/Output Schematics
      1. 6.10.1  Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger
      2. 6.10.2  Port P1, P1.6 and P1.7, Input/Output With Schmitt Trigger
      3. 6.10.3  Port P2, P2.0 and P2.4 to P2.5, Input/Output With Schmitt Trigger
      4. 6.10.4  Port P2, P2.1 to P2.3, Input/Output With Schmitt Trigger
      5. 6.10.5  Port P2, P2.6 and P2.7, Input/Output With Schmitt Trigger
      6. 6.10.6  Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger
      7. 6.10.7  Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger
      8. 6.10.8  Port P4, P4.0 to P4.5, Input/Output With Schmitt Trigger
      9. 6.10.9  Port P4, P4.6, Input/Output With Schmitt Trigger
      10. 6.10.10 Port P4, P4.7, Input/Output With Schmitt Trigger
      11. 6.10.11 Port P5, P5.0, Input/Output With Schmitt Trigger
      12. 6.10.12 Port P5, P5.1, Input/Output With Schmitt Trigger
      13. 6.10.13 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger
      14. 6.10.14 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger
      15. 6.10.15 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger
      16. 6.10.16 Port P6, P6.1, Input/Output With Schmitt Trigger
      17. 6.10.17 Port P6, P6.3, Input/Output With Schmitt Trigger
      18. 6.10.18 Port P6, P6.5, Input/Output With Schmitt Trigger
      19. 6.10.19 Port P6, P6.6, Input/Output With Schmitt Trigger
      20. 6.10.20 Port P6, P6.7, Input/Output With Schmitt Trigger
      21. 6.10.21 VeREF+/DAC0
      22. 6.10.22 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output
      23. 6.10.23 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
        1. 7.1.1.1 Development Kit
      2. 7.1.2 Device and Development Tool Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Related Links
      2. 7.2.2 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Device Overview

1.1 Features

  • Low Supply-Voltage Range, 1.8 V to 3.6 V
  • Ultra-Low Power Consumption
    • Active Mode: 300 µA at 1 MHz, 2.2 V
    • Standby Mode: 1.1 µA
    • Off Mode (RAM Retention): 0.1 µA
  • Five Power-Saving Modes
  • Wakeup From Standby Mode in Less Than 6 µs
  • 16-Bit RISC Architecture, 125-ns Instruction Cycle Time
  • Single-Channel Internal DMA
  • 12-Bit Analog-to-Digital Converter (ADC) With Internal Reference, Sample-and-Hold and Autoscan Feature
  • Three Configurable Operational Amplifiers
  • Dual 12-Bit Digital-to-Analog Converters (DACs) With Synchronization
  • 16-Bit Timer_A With Three Capture/Compare Registers
  • 16-Bit Timer_B With Three Capture/Compare-With-Shadow Registers
  • On-Chip Comparator
  • Serial Communication Interface (USART),
    Select Asynchronous UART or Synchronous SPI by Software
  • Brownout Detector
  • Supply-Voltage Supervisor and Monitor With Programmable Level Detection
  • Bootstrap Loader (BSL)
  • Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse
  • Integrated Liquid Crystal Display (LCD) Driver for up to 128 Segments
  • Available in 113-Ball BGA (ZCA) and 80-Pin QFP (PN) Packages
  • Section 3 Summarizes the Available Family Members
  • For Complete Module Descriptions, See the MSP430x4xx Family User's Guide (SLAU056)

1.2 Applications

  • Analog and Digital Sensor Systems
  • Digital Motor Control
  • Remote Controls
  • Thermostats
  • Digital Timers
  • Hand-Held Meters

1.3 Description

The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in less than 6 µs.

The MSP430FG43x devices are microcontrollers with two 16-bit timers, a high-performance 12-bit ADC, dual 12-bit DACs, three configurable operational amplifiers, one universal synchronous/asynchronous communication interface, DMA, 48 I/O pins, and an LCD driver.

Table 1-1 Device Information(1)

PART NUMBER PACKAGE BODY SIZE(2)
MSP430FG439PN LQFP (80) 12 mm x 12 mm
MSP430FG439ZCA BGA (113) 7 mm x 7 mm
(1) For the most current device, package, and ordering information, see the Package Option Addendum in Section 8, or see the TI web site at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 8.

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram.

fbd_slas380.gifFigure 1-1 Functional Block Diagram