SLAS380D April   2004  – November 2014 MSP430FG437 , MSP430FG438 , MSP430FG439

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3 Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Handling Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Supply Current Into AVCC + DVCC Excluding External Current
    5. 5.5  Schmitt-Trigger Inputs - Ports P1 to P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
    6. 5.6  Inputs Px.y, TAx, TBx
    7. 5.7  Leakage Current - Ports P1 to P6
    8. 5.8  Outputs - Ports P1 to P6
    9. 5.9  Output Frequency
    10. 5.10 Typical Characteristics - Outputs
    11. 5.11 Wake-Up From LPM3
    12. 5.12 RAM
    13. 5.13 LCD
    14. 5.14 Comparator_A
    15. 5.15 Comparator_A Typical Characteristics
    16. 5.16 Power-On Reset (POR) and Brownout Reset (BOR)
    17. 5.17 Supply Voltage Supervisor (SVS) and Supply Voltage Monitor (SVM)
    18. 5.18 DCO
    19. 5.19 Crystal Oscillator, XT1 Oscillator
    20. 5.20 Crystal Oscillator, XT2 Oscillator
    21. 5.21 USART0
    22. 5.22 12-Bit ADC, Power Supply and Input Range Conditions
    23. 5.23 12-Bit ADC, External Reference
    24. 5.24 12-Bit ADC, Built-In Reference
    25. 5.25 12-Bit ADC, Timing Parameters
    26. 5.26 12-Bit ADC, Linearity Parameters
    27. 5.27 12-Bit ADC, Temperature Sensor and Built-In VMID
    28. 5.28 12-Bit DAC, Supply Specifications
    29. 5.29 12-Bit DAC, Linearity Specifications
    30. 5.30 12-Bit DAC, Output Specifications
    31. 5.31 12-Bit DAC, Reference Input Specifications
    32. 5.32 12-Bit DAC, Dynamic Specifications
    33. 5.33 12-Bit DAC, Dynamic Specifications (Continued)
    34. 5.34 Operational Amplifier (OA), Supply Specifications
    35. 5.35 Operational Amplifier (OA), Input/Output Specifications
    36. 5.36 Operational Amplifier (OA), Dynamic Specifications
    37. 5.37 OA Dynamic Specifications Typical Characteristics
    38. 5.38 Flash Memory
    39. 5.39 JTAG Interface
    40. 5.40 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers (SFRs)
      1. 6.5.1 Interrupt Enable Registers 1 and 2
      2. 6.5.2 Interrupt Flag Registers 1 and 2
      3. 6.5.3 Module Enable Registers 1 and 2
    6. 6.6  Memory Organization
    7. 6.7  Bootstrap Loader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
      1. 6.9.1  DMA Controller
      2. 6.9.2  Oscillator and System Clock
      3. 6.9.3  Brownout, Supply Voltage Supervisor
      4. 6.9.4  Digital I/O
      5. 6.9.5  Basic Timer1
      6. 6.9.6  LCD Drive
      7. 6.9.7  OA
      8. 6.9.8  Watchdog Timer (WDT)
      9. 6.9.9  USART0
      10. 6.9.10 Timer_A3
      11. 6.9.11 Timer_B3
      12. 6.9.12 Comparator_A
      13. 6.9.13 ADC12
      14. 6.9.14 DAC12
      15. 6.9.15 Peripheral File Map
    10. 6.10 Input/Output Schematics
      1. 6.10.1  Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger
      2. 6.10.2  Port P1, P1.6 and P1.7, Input/Output With Schmitt Trigger
      3. 6.10.3  Port P2, P2.0 and P2.4 to P2.5, Input/Output With Schmitt Trigger
      4. 6.10.4  Port P2, P2.1 to P2.3, Input/Output With Schmitt Trigger
      5. 6.10.5  Port P2, P2.6 and P2.7, Input/Output With Schmitt Trigger
      6. 6.10.6  Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger
      7. 6.10.7  Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger
      8. 6.10.8  Port P4, P4.0 to P4.5, Input/Output With Schmitt Trigger
      9. 6.10.9  Port P4, P4.6, Input/Output With Schmitt Trigger
      10. 6.10.10 Port P4, P4.7, Input/Output With Schmitt Trigger
      11. 6.10.11 Port P5, P5.0, Input/Output With Schmitt Trigger
      12. 6.10.12 Port P5, P5.1, Input/Output With Schmitt Trigger
      13. 6.10.13 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger
      14. 6.10.14 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger
      15. 6.10.15 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger
      16. 6.10.16 Port P6, P6.1, Input/Output With Schmitt Trigger
      17. 6.10.17 Port P6, P6.3, Input/Output With Schmitt Trigger
      18. 6.10.18 Port P6, P6.5, Input/Output With Schmitt Trigger
      19. 6.10.19 Port P6, P6.6, Input/Output With Schmitt Trigger
      20. 6.10.20 Port P6, P6.7, Input/Output With Schmitt Trigger
      21. 6.10.21 VeREF+/DAC0
      22. 6.10.22 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output
      23. 6.10.23 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
        1. 7.1.1.1 Development Kit
      2. 7.1.2 Device and Development Tool Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Related Links
      2. 7.2.2 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Voltage applied at VCC to VSS –0.3 4.1 V
Voltage applied to any pin(2) –0.3 VCC + 0.3 V
Diode current at any device terminal ±2 mA
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS.The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TDI/TCLK pin when blowing the JTAG fuse.

5.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range Unprogrammed device -55 150 °C
Programmed device -40 85

5.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Supply voltage(1)
(AVCC = DVCC1 = DVCC2 = VCC)
During program execution 1.8 3.6 V
During program execution,
SVS enabled and PORON = 1(2)
2 3.6
During flash memory programming 2.7 3.6
VSS Supply voltage(1)
(AVSS = DVSS1 = DVSS2 = VSS)
0 0 V
TA Operating free-air temperature range –40 85 °C
f(LFXT1) XT1 crystal frequency(3) LF selected, XTS_FLL = 0 Watch crystal 32.768 kHz
XT1 selected, XTS_FLL = 1 Ceramic resonator 450 8000
XT1 selected, XTS_FLL = 1 Crystal 1000 8000
f(XT2) XT2 crystal frequency Ceramic resonator 450 8000 kHz
Crystal 1000 8000
f(System) Processor frequency (signal MCLK) VCC = 1.8 V dc 4.15 MHz
VCC = 3.6 V dc 8
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power up and operation.
(2) The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS circuitry.
(3) In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
freq_vs_supplyvoltage_slas380.gifFigure 5-1 Frequency vs Supply Voltage, Typical Characteristic

5.4 Supply Current Into AVCC + DVCC Excluding External Current

over recommended operating free-air temperature (unless otherwise noted)
PARAMETER TA VCC MIN TYP MAX UNIT
I(AM) Active mode(1)
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32768 Hz,
XTS_FLL = 0, SELM = (0,1)
–40°C to 85°C 2.2 V 300 370 µA
3 V 470 570
I(LPM0) Low-power mode (LPM0)(1)(4) –40°C to 85°C 2.2 V 55 70 µA
3 V 95 110
I(LPM2) Low-power mode (LPM2),
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32768 Hz, SCG0 = 0(2)(4)
–40°C to 85°C 2.2 V 11 14 µA
3 V 17 22
I(LPM3) Low-power mode (LPM3)
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32768 Hz, SCG0 = 1(2)(3)(4)
–40°C 2.2 V 1 2 µA
25°C 1.1 2
60°C 2 3
85°C 3.5 6
–40°C 3 V 1.8 2.8
25°C 1.6 2.7
60°C 2.5 3.5
85°C 4.2 7.5
I(LPM4) Low-power mode (LPM4)
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 0 Hz, SCG0 = 1(2)(4)
–40°C 2.2 V 0.1 0.5 µA
25°C 0.1 0.5
60°C 0.7 1.1
85°C 1.7 3
–40°C 3 V 0.1 0.8
25°C 0.1 0.8
60°C 0.8 1.2
85°C 1.9 3.5
(1) Timer_B is clocked by f(DCOCLK) = f(DCO) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(3) The current consumption in LPM3 is measured with active Basic Timer1 and LCD (ACLK selected). The current consumption of the Comparator_A and the SVS module are specified in the respective sections. The LPM3 currents are characterized with a KDS Daishinku DT−38 (6 pF) crystal and OSCCAPx = 01h.
(4) Current for brownout included.

Current consumption of active mode versus system frequency:

I(AM) = I(AM) [1 MHz] × f(System) [MHz]

Current consumption of active mode versus supply voltage:

I(AM) = I(AM) [3 V] + 175 µA/V × (VCC – 3 V)

5.5 Schmitt-Trigger Inputs – Ports P1 to P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VCC MIN MAX UNIT
VIT+ Positive-going input threshold voltage 2.2 V 1.1 1.55 V
3 V 1.5 1.98
VIT– Negative-going input threshold voltage 2.2 V 0.4 0.9 V
3 V 0.9 1.3
Vhys Input voltage hysteresis (VIT+ – VIT– ) 2.2 V 0.3 1.1 V
3 V 0.5 1

5.6 Inputs Px.y, TAx, TBx

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
t(int) External interrupt timing Port P1, P2: P1.x to P2.x, external trigger signal for the interrupt flag(1) 2.2 V 62 ns
3 V 50
t(cap) Timer_A or Timer_B capture timing TA0, TA1, TA2
TB0, TB1, TB2
2.2 V 62 ns
3 V 50
f(TAext) Timer_A or Timer_B clock frequency externally applied to pin TACLK, TBCLK, INCLK: t(H) = t(L) 2.2 V 8 MHz
f(TBext) 3 V 10
f(TAint) Timer_A or Timer_B clock frequency SMCLK or ACLK signal selected 2.2 V 8 MHz
f(TBint) 3 V 10
(1) The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It might be set with trigger signals shorter than t(int).

5.7 Leakage Current – Ports P1 to P6(1)

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Ilkg(Px.y) Leakage current, Port Px V(Px.y)(2) VCC = 2.2 V, 3 V ±50 nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The port pin must be selected as input.

5.8 Outputs – Ports P1 to P6

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VOH High-level output voltage IOH(max) = –1.5 mA, VCC = 2.2 V(1) VCC – 0.25 VCC V
IOH(max) = –6 mA, VCC = 2.2 V(2) VCC – 0.6 VCC
IOH(max) = –1.5 mA, VCC = 3 V(1) VCC – 0.25 VCC
IOH(max) = –6 mA, VCC = 3 V(2) VCC – 0.6 VCC
VOL Low-level output voltage IOL(max) = 1.5 mA, VCC = 2.2 V(1) VSS VSS + 0.25 V
IOL(max) = 6 mA, VCC = 2.2 V(2) VSS VSS + 0.6
IOL(max) = 1.5 mA, VCC = 3 V(1) VSS VSS + 0.25
IOL(max) = 6 mA, VCC = 3 V(2) VSS VSS + 0.6
(1) The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum specified voltage drop.
(2) The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum specified voltage drop.

5.9 Output Frequency

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(Px.y) (1 ≤ × ≤ 6, 0 ≤ y ≤ 7) CL = 20 F,
IL = ±1.5 mA
VCC = 2.2 V, 3 V dc f(System) MHz
f(MCLK) P1.1/TA0/MCLK CL = 20 pF f(System) MHz
f(SMCLK) P1.4/TBCLK/SMCLK
f(ACLK) P1.5/TACLK/ACLK
t(Xdc) Duty cycle of output frequency P1.5/TACLK/ACLK,
CL = 20 pF,
VCC = 2.2 V, 3 V
f(ACLK) = f(LFXT1) = f(XT1) 40% 60%
f(ACLK) = f(LFXT1) = f(LF) 30% 70%
f(ACLK) = f(LFXT1) 50%
P1.1/TA0/MCLK,
CL = 20 pF,
VCC = 2.2 V, 3 V
f(MCLK) = f(XT1) 40% 60%
f(MCLK) = f(DCOCLK) 50% –
15 ns
50% 50%+
15 ns
P1.4/TBCLK/SMCLK,
CL = 20 pF,
VCC = 2.2 V, 3 V
f(SMCLK) = f(XT2) 40% 60%
f(SMCLK) = f(DCOCLK) 50% –
15 ns
50% 50%+
15 ns

5.10 Typical Characteristics – Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
g_iol_vol_2p2v_slas380.gifFigure 5-2 Typical Low-Level Output Current vs Typical Low-Level Output Current
g_ioh_voh_2p2v_slas380.gifFigure 5-4 Typical High-Level Output Current vs Typical High-Level Output Current
g_iol_vol_3v_slas380.gifFigure 5-3 Typical Low-Level Output Current vs Typical Low-Level Output Current
g_ioh_voh_3v_slas380.gifFigure 5-5 Typical High-Level Output Current vs Typical High-Level Output Current

5.11 Wake-Up From LPM3

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
td(LPM3) Delay time f = 1 MHz VCC = 2.2 V, 3 V 6 µs
f = 2 MHz 6
f = 3 MHz 6

5.12 RAM

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VRAMh CPU halted(1) 1.6 V
(1) This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution should take place during this supply voltage condition.

5.13 LCD

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(33) Analog voltage Voltage at P5.7/R33 VCC = 3 V 2.5 VCC + 0.2 V
V(23) Voltage at P5.6/R23 [V(33)−V(03)] × 2/3 + V(03)
V(13) Voltage at P5.5/R13 [V(33)−V(03)] × 1/3 + V(03)
V(33)-V(03) Voltage at R33 to R03 2.5 VCC + 0.2
I(R03) Input leakage R03 = VSS No load at all segment and common lines, VCC = 3 V ±20 nA
I(R13) P5.5/R13 = VCC/3 ±20
I(R23) P5.6/R23 = 2 × VCC/3 ±20
V(Sxx0) Segment line voltage I(Sxx) = −3 µA, VCC = 3 V V(03) V(03) - 1 V
V(Sxx1) V(13) V(13) - 1
V(Sxx2) V(23) V(23) - 1
V(Sxx3) V(33) V(33) - 1

5.14 Comparator_A(1)

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
I(CC) CAON = 1, CARSEL = 0, CAREF = 0 2.2 V 25 40 µA
3 V 45 60
I(Refladder/RefDiode) CAON = 1, CARSEL = 0, CAREF = (1,2,3),
No load at P1.6/CA0 and P1.7/CA1
2.2 V 30 50 µA
3 V 45 71
V(Ref025) (Voltage at 0.25 VCC node) / VCC PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at P1.6/CA0 and P1.7/CA1
2.2 V, 3 V 0.23 0.24 0.25
V(Ref050) (Voltage at 0.55 VCC node) / VCC PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at P1.6/CA0 and P1.7/CA1
2.2 V, 3 V 0.47 0.48 0.5
V(RefVT) See Figure 5-6 and Figure 5-7 PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at P1.6/CA0 and P1.7/CA1,
TA = 85°C
2.2 V 390 480 540 mV
3 V 400 490 550
VIC Common-mode input voltage range CAON = 1 2.2 V, 3 V 0 VCC –1 V
Vp – VS Offset voltage See (2) 2.2 V, 3 V –30 30 mV
Vhys Input hysteresis CAON = 1 2.2 V, 3 V 0 0.7 1.4 mV
t(response LH) TA = 25°C,
Overdrive 10 mV, without filter: CAF = 0
2.2 V 160 210 300 ns
3 V 80 150 240
TA = 25°C,
Overdrive 10 mV, with filter: CAF = 1
2.2 V 1.4 1.9 3.4 µs
3 V 0.9 1.5 2.6
t(response HL) TA = 25°C,
Overdrive 10 mV, without filter: CAF = 0
2.2 V 130 210 300 ns
3 V 80 150 240
TA = 25°C,
Overdrive 10 mV, with filter: CAF = 1
2.2 V 1.4 1.9 3.4 µs
3 V 0.9 1.5 2.6
(1) The leakage current for the Comparator_A terminals is identical to Ilkg(Px.y) specification.
(2) The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together.

5.15 Comparator_A Typical Characteristics

slas508_graph5.gifFigure 5-6 Reference Voltage vs Free-Air Temperature
slas508_graph6.gifFigure 5-7 Reference Voltage vs Free-Air Temperature
slas508_bd_comA.gifFigure 5-8 Block Diagram of Comparator_A Module
slas508_overdrive.gifFigure 5-9 Overdrive Definition

5.16 Power-On Reset (POR) and Brownout Reset (BOR)(1)

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(BOR) Brownout(2) 2000 µs
VCC(start) dVCC/dt ≤ 3 V/s (see Figure 5-10) 0.7 × V(B_IT– ) V
V(B_IT–) dVCC/dt ≤ 3 V/s (see Figure 5-10 through Figure 5-12) 1.71 V
Vhys(B_IT–) dVCC/dt ≤ 3 V/s (see Figure 5-10) 70 130 210 mV
t(reset) Pulse length needed at RST/NMI pin to accepted reset internally, VCC = 2.2 V, 3 V 2 µs
(1) The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–) + Vhys(B_IT–) is ≤ 1.8 V.
(2) During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT–) + Vhys(B_IT–). The default FLL+ settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. See the MSP430x4xx Family User's Guide (SLAU056) for more information on the brownout/SVS circuit.
slas508_porreset_supvol.gifFigure 5-10 POR and BOR vs Supply Voltage
slas508_vcc_drop_level.gifFigure 5-11 VCC(drop) Level with a Square Voltage Drop to Generate a POR or BOR Signal
slas508_vcc_dop_level2.gifFigure 5-12 VCC(drop) Level With a Triangle Voltage Drop to Generate a POR or BOR Signal

5.17 Supply Voltage Supervisor (SVS) and Supply Voltage Monitor (SVM)

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t(SVSR) dVCC/dt > 30 V/ms (see Figure 5-13) 5 150 µs
dVCC/dt ≤ 30 V/ms 2000
td(SVSon) SVS on, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V 150 300 µs
tsettle VLD ≠ 0(2) 12 µs
V(SVSstart) VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 5-13) 1.55 1.7 V
Vhys(SVS_IT–) VCC/dt ≤ 3 V/s (see Figure 5-13) VLD = 1 70 120 155 mV
VLD = 2 to 14 V(SVS_IT–) × 0.001 V(SVS_IT–) × 0.016
VCC/dt ≤ 3 V/s (see Figure 5-13),
external voltage applied on A7
VLD = 15 4.4 20 mV
V(SVS_IT–) VCC/dt ≤ 3 V/s (see Figure 5-13) VLD = 1 1.8 1.9 2.05 V
VLD = 2 1.94 2.1 2.23
VLD = 3 2.05 2.2 2.35
VLD = 4 2.14 2.3 2.46
VLD = 5 2.24 2.4 2.58
VLD = 6 2.33 2.5 2.69
VLD = 7 2.46 2.65 2.84
VLD = 8 2.58 2.8 2.97
VLD = 9 2.69 2.9 3.10
VLD = 10 2.83 3.05 3.26
VLD = 11 2.94 3.2 3.39
VLD = 12 3.11 3.35 3.58(1)
VLD = 13 3.24 3.5 3.73(1)
VLD = 14 3.43 3.7(1) 3.96(1)
VCC/dt ≤ 3 V/s (see Figure 5-13),
external voltage applied on A7
VLD = 15 1.1 1.2 1.3
ICC(SVS)(3) VLD ≠ 0, VCC = 2.2 V, 3 V 10 15 µA
(1) The recommended operating voltage range is limited to 3.6 V.
(2) tsettle is the settling time that the comparator output needs to have a stable level after VLD is switched from VLD ≠ 0 to a different VLD value somewhere between 2 and 15. The overdrive is assumed to be > 50 mV.
(3) The current consumption of the SVS module is not included in the ICC current consumption data.
slas508_svsreset_supvol.gifFigure 5-13 SVS Reset (SVSR) vs Supply Voltage
slas508_vcc_drop_level3.gifFigure 5-14 VCC(drop) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal

5.18 DCO

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
f(DCOCLK) N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0, fCrystal = 32.738 kHz 2.2 V, 3 V 1 MHz
f(DCO=2) FN_8=FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1 2.2 V 0.3 0.65 1.25 MHz
3 V 0.3 0.7 1.3
f(DCO=27) FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1 2.2 V 2.5 5.6 10.5 MHz
3 V 2.7 6.1 11.3
f(DCO=2) FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1 2.2 V 0.7 1.3 2.3 MHz
3 V 0.8 1.5 2.5
f(DCO=27) FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1 2.2 V 5.7 10.8 18 MHz
3 V 6.5 12.1 20
f(DCO=2) FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1 2.2 V 1.2 2 3 MHz
3 V 1.3 2.2 3.5
f(DCO=27) FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1 2.2 V 9 15.5 25 MHz
3 V 10.3 17.9 28.5
f(DCO=2) FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1 2.2 V 1.8 2.8 4.2 MHz
3 V 2.1 3.4 5.2
f(DCO=27) FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1 2.2 V 13.5 21.5 33 MHz
3 V 16 26.6 41
f(DCO=2) FN_8 = 1, FN_4 = FN_3 = FN_2 = x, DCOPLUS = 1 2.2 V 2.8 4.2 6.2 MHz
3 V 4.2 6.3 9.2
f(DCO=27) FN_8 = 1, FN_4 = FN_3 = FN_2 = x, DCOPLUS = 1 2.2 V 21 32 46 MHz
3 V 30 46 70
Sn Step size between adjacent DCO taps:
Sn = fDCO(Tap n+1) / fDCO(Tap n) (see Figure 5-16 for taps 21 to 27)
1 < TAP ≤ 20 1.06 1.11
TAP = 27 1.07 1.17
Dt Temperature drift, N(DCO) = 01Eh,
FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0
2.2 V –0.2 –0.3 –0.4 %/°C
3 V –0.2 –0.3 –0.4
DV Drift with VCC variation, N(DCO) = 01Eh,
FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0
2.2 V, 3 V 0 5 15 %/V
slas508_fre_supvol_ambtemp.gifFigure 5-15 DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
slas508_dcotap.gifFigure 5-16 DCO Tap Step Size
slas508_overlap_DCOranges.gifFigure 5-17 Five Overlapping DCO Ranges Controlled by FN_x Bits

5.19 Crystal Oscillator, XT1 Oscillator(1)(2)

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CXIN Integrated input capacitance(4) OSCCAPx = 0h, VCC = 2.2 V, 3 V 0 pF
OSCCAPx = 1h, VCC = 2.2 V, 3 V 10
OSCCAPx = 2h, VCC = 2.2 V, 3 V 14
OSCCAPx = 3h, VCC = 2.2 V, 3 V 18
CXOUT Integrated output capacitance(4) OSCCAPx = 0h, VCC = 2.2 V, 3 V 0 pF
OSCCAPx = 1h, VCC = 2.2 V, 3 V 10
OSCCAPx = 2h, VCC = 2.2 V, 3 V 14
OSCCAPx = 3h, VCC = 2.2 V, 3 V 18
VIL Input levels at XIN VCC = 2.2 V, 3 V(3) VSS 0.2 × VCC V
VIH 0.8 × VCC VCC
(1) The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is (CXIN × CXOUT) / (CXIN+ CXOUT). This is independent of XTS_FLL.
(2) To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
  • Keep the trace between the device and the crystal as short as possible.
  • Design a good ground plane around the oscillator pins.
  • Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
  • Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
  • Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
  • If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
  • Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter.
(3) Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
(4) External capacitance is recommended for precision real-time clock applications, OSCCAPx = 0h.

5.20 Crystal Oscillator, XT2 Oscillator(1)

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CXT2IN Integrated input capacitance VCC = 2.2 V, 3 V 2 pF
CXT2OUT Integrated output capacitance VCC = 2.2 V, 3 V 2 pF
VIL Input levels at XT2IN VCC = 2.2 V, 3 V(2) VSS 0.2 × VCC V
VIH 0.8 × VCC VCC V
(1) The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
(2) Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.

5.21 USART0(1)

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t(τ) USART0 deglitch time VCC = 2.2 V, SYNC = 0, UART mode 200 430 800 ns
VCC = 3 V, SYNC = 0, UART mode 150 280 500
(1) The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t(τ) to ensure that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum timing condition of t(τ). The operating conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD0 line.

5.22 12-Bit ADC, Power Supply and Input Range Conditions(1)

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AVCC Analog supply voltage AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
2.2 3.6 V
V(P6.x/Ax) Analog input voltage range(2) All external Ax terminals, Analog inputs selected in ADC12MCTLx register and P6Sel.x = 1,
V(AVSS) ≤ VAx ≤ V(AVCC)
0 VAVCC V
IADC12 Operating supply current into the AVCC terminal(3) fADC12CLK = 5.0 MHz,
ADC12ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC12DIV = 0
VCC = 2.2 V 0.65 1.3 mA
VCC = 3 V 0.8 1.6
IREF+ Operating supply current into the AVCC terminal(4) fADC12CLK = 5.0 MHz,
ADC12ON = 0,
REFON = 1, REF2_5V = 1
VCC = 3 V 0.5 0.8 mA
fADC12CLK = 5.0 MHz,
ADC12ON = 0
REFON = 1, REF2_5V = 0
VCC = 2.2 V 0.5 0.8 mA
VCC = 3 V 0.5 0.8
CI Input capacitance Only one terminal can be selected at one time, Ax VCC = 2.2 V 40 pF
RI Input MUX ON resistance 0 V ≤ VAx ≤ VAVCC VCC = 3 V 2000 Ω
(1) The leakage current is defined in the leakage current table with Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
(3) The internal reference supply current is not included in current consumption parameter IADC12.
(4) The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.

5.23 12-Bit ADC, External Reference(1)

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VeREF+ Positive external reference voltage input VeREF+ > VREF–/VeREF–(2) 1.4 VAVCC V
VREF–/VeREF– Negative external reference voltage input VeREF+ > VREF–/VeREF–(3) 0 1.2 V
(VeREF+
VREF–/VeREF–)
Differential external reference voltage input VeREF+ > VREF–/VeREF–(4) 1.4 VAVCC V
IVeREF+ Static input current 0 V ≤ VeREF+ ≤ VAVCC VCC = 2.2 V, 3 V ±1 µA
IVREF–/VeREF– Static input current 0 V ≤ VeREF– ≤ VAVCC VCC = 2.2 V, 3 V ±1 µA
(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements.

5.24 12-Bit ADC, Built-In Reference

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VREF+ Positive built in reference voltage output REF2_5V = 1 for 2.5 V,
IVREF+max ≤ IVREF+ ≤ IVREF+min
3 V 2.4 2.5 2.6 V
REF2_5V = 0 for 1.5 V,
IVREF+max ≤ IVREF+ ≤ IVREF+min
2.2 V, 3 V 1.44 1.5 1.56
AVCC(min) AVCC minimum voltage, Positive built in reference active REF2_5V = 0,
IVREF+max ≤ IVREF+ ≤ IVREF+min
2.2 V
REF2_5V = 1,
IVREF+min ≥ IVREF+ ≥ –0.5 mA
2.8
REF2_5V = 1,
IVREF+min ≥ IVREF+ ≥ – 1 mA
2.9
IVREF+ Load current out of VREF+ terminal 2.2 V 0.01 –0.5 mA
3 V 0.01 –1
IL(VREF)+ Load-current regulation, VREF+ terminal IVREF+ = 500 µA ± 100 µA,
Analog input voltage ≈ 0.75 V,
REF2_5V = 0
2.2 V ±2 LSB
3 V ±2
IVREF+ = 500 µA ± 100 µA,
Analog input voltage ≈ 1.25 V,
REF2_5V = 1
3 V ±2 LSB
IDL(VREF)+ Load current regulation, VREF+ terminal IVREF+ = 100 µA → 900 µA,
CVREF+ = 5 µF, ax ≈ 0.5 × VREF+,
Error of conversion result ≤ 1 LSB
3 V 20 ns
CVREF+ Capacitance at pin VREF+(1) REFON =1,
0 mA ≤ IVREF+ ≤ IVREF+max
2.2 V, 3 V 5 10 µF
TREF+ Temperature coefficient of built-in reference IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ 1 mA
2.2 V, 3 V ±100 ppm/°C
tREFON Settle time of internal reference voltage (see Figure 5-18 ) (2) IVREF+ = 0.5 mA, CVREF+ = 10 µF,
VREF+ = 1.5 V, VAVCC = 2.2 V
17 ms
(1) The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two capacitors between pins VREF+ and AVSS and VREF-–/VeREF– and AVSS: 10 µF tantalum and 100 nF ceramic.
(2) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external capacitive load.
slas508_typ_settime_extcap.gifFigure 5-18 Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
adc_supply_voltage_external_slas380.gifFigure 5-19 Supply Voltage and Reference Voltage Design VREF–/VeREF– External Supply
adc_supply_voltage_internal_slas380.gifFigure 5-20 Supply Voltage and Reference Voltage Design VREF–/VeREF– = AVSS, Internally Connected

5.25 12-Bit ADC, Timing Parameters

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fADC12CLK ADC12 clock frequency For specified performance of ADC12 linearity parameters 2.2 V, 3 V 0.45 5 6.3 MHz
fADC12OSC Internal ADC12 oscillator ADC12DIV = 0, fADC12CLK = fADC12OSC 2.2 V, 3 V 3.7 5 6.3 MHz
tCONVERT Conversion time CVREF+ ≥ 5 µF, Internal oscillator,
fADC12OSC = 3.7 MHz to 6.3 MHz
2.2 V, 3 V 2.06 3.51 µs
External fADC12CLK from ACLK, MCLK, or SMCLK, ADC12SSEL ≠ 0 13 × ADC12DIV ×
1/fADC12CLK
µs
tADC12ON Turn on settling time of the ADC See (1) 100 ns
tSample Sampling time RS = 400 Ω,RI = 1000 Ω,
CI = 30 pF, τ = [RS +RI] × CI(2)
3 V 1220 ns
2.2 V 1400
(1) The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already settled.
(2) Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) × (RS + RI) x CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance.

5.26 12-Bit ADC, Linearity Parameters

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
EI Integral linearity error 1.4 V ≤ (VeREF+ – VREF–/VeREF–) min ≤ 1.6 V 2.2 V, 3 V ±2 LSB
1.6 V < (VeREF+ – VREF–/VeREF–) min ≤ VAVCC ±1.7
ED Differential linearity error (VeREF+ – VREF–/VeREF–) min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V ±1 LSB
EO Offset error (VeREF+ – VREF–/VeREF–) min ≤ (VeREF+ – VREF–/VeREF–),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V ±2 ±4 LSB
EG Gain error (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ =10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V ±1.1 ±2 LSB
ET Total unadjusted error (VeREF+ – VREF–/VeREF– )min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V ±2 ±5 LSB

5.27 12-Bit ADC, Temperature Sensor and Built-In VMID

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
ISENSOR Operating supply current into AVCC terminal(1) REFON = 0, INCH = 0Ah,
ADC12ON = NA, TA = 25°C
2.2 V 40 120 µA
3 V 60 160
VSENSOR See  (2)  ADC12ON = 1, INCH = 0Ah,
TA = 0°C
2.2 V, 3 V 986 mV
TCSENSOR ADC12ON = 1, INCH = 0Ah 2.2 V, 3 V 3.55 ± 3% mV/°C
tSENSOR(sample) Sample time required if channel 10 is selected(3) ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
2.2 V 30 µs
3 V 30
IVMID Current into divider at channel 11(4) ADC12ON = 1, INCH = 0Bh 2.2 V NA µA
3 V NA
VMID AVCC divider at channel 11 ADC12ON = 1, INCH = 0Bh,
VMID ≈ 0.5 × VAVCC
2.2 V 1.1 1.10 ± 0.04 V
3 V 1.5 1.50 ± 0.04
tVMID(sample) Sample time required if channel 11 is selected(5) ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V 1400 ns
3 V 1220
(1) The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON = 1), or (ADC12ON = 1 AND INCH = 0Ah and sample signal is high). When REFON = 1, ISENSOR is already included in IREF+.
(2) The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended in order to minimize the offset error of the built-in temperature sensor.
(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
(4) No additional current is needed. The VMID is used during sampling.
(5) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.

5.28 12-Bit DAC, Supply Specifications

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC Analog supply voltage AVCC = DVCC, AVSS = DVSS = 0 V 2.2 3.6 V
IDD Supply current, single DAC channel(1)(2) DAC12AMPx = 2, DAC12IR = 0,
DAC12_xDAT = 0800h
2.2 V, 3 V 50 110 µA
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = 0800h , VeREF+ = VREF+ = AVCC
50 110
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0800h, VeREF+ = VREF+ = AVCC
200 440
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0800h, VeREF+ = VREF+ = AVCC
700 1500
PSRR Power-supply rejection ratio(3)(4) DAC12_xDAT = 0800h, VREF = 1.5 V,
ΔAVCC = 100 mV
2.2 V 70 dB
DAC12_xDAT = 0800h, VREF = 1.5 V or 2.5 V,
ΔAVCC = 100 mV
3 V
(1) No load at the output pin, DAC0 or DAC1, assuming that the control bits for the shared pins are set properly.
(2) Current into reference terminals not included. If DAC12IR = 1, current flows through the input divider (see Reference Input specifications).
(3) PSRR = 20 × log(ΔAVCC / ΔVDAC12_xOUT).
(4) VREF is applied externally. The internal reference is not used.

5.29 12-Bit DAC, Linearity Specifications

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5-21)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Resolution 12-bit monotonic 12 bits
INL Integral nonlinearity(1) Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V ±2.0 ±8.0 LSB
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3 V
DNL Differential nonlinearity(1) Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V ±0.4 ±1.0 LSB
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3 V
EO Offset voltage without calibration(1)(2) Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V ±21 mV
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3 V
Offset voltage with calibration(1)(2) Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V ±2.5
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3 V
dE(O)/dT Offset error temperature coefficient(1) 2.2 V, 3 V ±30 µV/°C
EG Gain error(1) VREF = 1.5 V 2.2 V ±3.5 %FSR
VREF = 2.5 V 3 V
dE(G)/dT Gain temperature coefficient(1) 2.2 V, 3 V 10 ppm of
FSR/°C
tOffset Cal Time for offset calibration(3) DAC12AMPx = 2 2.2 V, 3 V 100 ms
DAC12AMPx = 3, 5 32
DAC12AMPx = 4, 6, 7 6
(1) Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b" of the first-order equation: y = a + b × x. VDAC12_xOUT = EO + (1 + EG) × (VeREF+ / 4095) × DAC12_xDAT, DAC12IR = 1.
(2) The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON.
(3) The offset calibration can be done if DAC12AMPx = \{2, 3, 4, 5, 6, 7\}. The output operational amplifier is switched off with DAC12AMPx = \{0, 1\}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may affect accuracy and is not recommended.
slas508_lin_test_gain.gifFigure 5-21 Linearity Test Load Conditions and Gain/Offset Definition
g_dac_inlerror_inputdata_slas380.gifFigure 5-22 Typical INL Error vs Digital Input Data
g_dac_dnlerror_inputdata_slas380.gifFigure 5-23 Typical DNL Error vs Digital Input Data

5.30 12-Bit DAC, Output Specifications

over recommended operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VO Output voltage range(1) (see Figure 5-24) No Load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
2.2 V, 3 V 0 0.005 V
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
AVCC – 0.05 AVCC
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
0 0.1
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
AVCC – 0.13 AVCC
CL(DAC12) Maximum DAC12 load capacitance 2.2 V, 3 V 100 pF
IL(DAC12) Maximum DAC12 load current 2.2 V –0.5 +0.5 mA
3 V –1.0 +1.0
RO/P(DAC12) Output resistance (see Figure 5-24) RLoad = 3 kΩ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 7, DAC12_xDAT = 0h
2.2 V, 3 V 150 250 Ω
RLoad = 3 kΩ,
VO/P(DAC12) > AVCC – 0.3 V,
DAC12AMPx = 7, DAC12_xDAT = 0FFFh
150 250
RLoad = 3 kΩ,
0.3 V ≤ VO/P(DAC12) ≤ AVCC – 0.3 V
DAC12AMPx = 7
1 4
(1) Data is valid after the offset calibration of the output amplifier.
slas508_output_res_tests.gifFigure 5-24 DAC12_x Output Resistance Tests

5.31 12-Bit DAC, Reference Input Specifications

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VeREF+ Reference input voltage range DAC12IR = 0(1)(2) 2.2 V, 3 V AVCC / 3 AVCC + 0.2 V
DAC12IR = 1(3)(4) AVCC AVCC + 0.2
Ri(VREF+),
(Ri(VeREF+)
Reference input resistance DAC12_0 IR = DAC12_1 IR = 0 2.2 V, 3 V 20
DAC12_0 IR = 1, DAC12_1 IR = 0 40 48 56
DAC12_0 IR = 0, DAC12_1 IR = 1 40 48 56
DAC12_0 IR = DAC12_1 IR =1,
DAC12_0 SREFx = DAC12_1 SREFx(5)
20 24 28
(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
(2) The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / [3 × (1 + EG)].
(3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
(4) The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / (1 + EG).
(5) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel, reducing the reference input resistance.

5.32 12-Bit DAC, Dynamic Specifications

Vref = VCC, DAC12IR = 1, over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5-25 and Figure 5-26)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
tON DAC12 on time DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB(1)
(see Figure 5-25)
DAC12AMPx = 0 → \{2, 3, 4\} 2.2 V, 3 V 60 120 µs
DAC12AMPx = 0 → \{5, 6\} 15 30
DAC12AMPx = 0 → 7 6 12
tS(FS) Settling time,
full scale
DAC12_xDAT =
80h→F7Fh→80h
DAC12AMPx = 2 2.2 V, 3 V 100 200 µs
DAC12AMPx = 3, 5 40 80
DAC12AMPx = 4, 6, 7 15 30
tS(C–C) Settling time,
code to code
DAC12_xDAT =
3F8h→408h→3F8h
BF8h→C08h→BF8h
DAC12AMPx = 2 2.2 V, 3 V 5 µs
DAC12AMPx = 3, 5 2
DAC12AMPx = 4, 6, 7 1
SR Slew rate DAC12_xDAT =
80h→ F7Fh→ 80h(2)
DAC12AMPx = 2 2.2 V, 3 V 0.05 0.12 V/µs
DAC12AMPx = 3, 5 0.35 0.7
DAC12AMPx = 4, 6, 7 1.5 2.7
Glitch energy,
full scale
DAC12_xDAT =
80h→ F7Fh→ 80h
DAC12AMPx = 2 2.2 V, 3 V 10 nV-s
DAC12AMPx = 3, 5 10
DAC12AMPx = 4, 6, 7 10
(1) RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 5-25.
(2) Slew rate applies to output voltage steps ≥ 200 mV.
slas508_settling_glitch_testing.gifFigure 5-25 Settling Time and Glitch Energy Testing
slas508_slew_rate_test.gifFigure 5-26 Slew Rate Testing

5.33 12-Bit DAC, Dynamic Specifications (Continued)

TA = 25°C unless otherwise noted
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
BW–3dB 3-dB bandwidth,
VDC = 1.5 V, VAC = 0.1 VPP
(see Figure 5-27)
DAC12AMPx = \{2, 3, 4\}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
2.2 V, 3 V 40 kHz
DAC12AMPx = \{5, 6\}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
180
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
550
Channel-to-channel crosstalk(1)
(see Figure 5-28)
DAC12_0DAT = 800h, No Load,
DAC12_1DAT = 80h↔F7Fh, RLoad = 3 kΩ
fDAC12_1OUT = 10 kHz with 50/50 duty cycle
2.2 V, 3 V –80 dB
DAC12_0DAT = 80h↔F7Fh, RLoad = 3 kΩ,
DAC12_1DAT = 800h, No Load,
fDAC12_0OUT = 10 kHz with 50/50 duty cycle
–80
(1) RLOAD = 3 kΩ, CLOAD = 100 pF
slas508_test_bad_spec.gifFigure 5-27 Test Conditions for 3-dB Bandwidth Specification
slas508_crosstalk.gifFigure 5-28 Crosstalk Test Conditions

5.34 Operational Amplifier (OA), Supply Specifications

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VCC Supply voltage 2.2 3.6 V
ICC Supply current(1) Fast Mode, RRIP OFF 2.2 V, 3 V 180 290 µA
Medium Mode, RRIP OFF 110 190
Slow Mode, RRIP OFF 50 80
Fast Mode, RRIP ON 300 490
Medium Mode, RRIP ON 190 350
Slow Mode, RRIP ON 90 190
PSRR Power supply rejection ratio Non-inverting 2.2 V, 3 V 70 dB
(1) P6SEL.x = 1 for each corresponding pin when used in OA input or OA output mode.

5.35 Operational Amplifier (OA), Input/Output Specifications

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VI/P Voltage supply, I/P RRIP OFF –0.1 VCC – 1.2 V
RRIP ON –0.1 VCC + 0.1
IIkg Input leakage current, I/P(1)(2) TA = –40°C to +55°C –5 ±0.5 5 nA
TA = +55°C to +85°C –20 ±5 20
Vn Voltage noise density, I/P Fast Mode fV(I/P) = 1 kHz 50 nV/√Hz
Medium Mode 80
140
Slow Mode
Fast Mode fV(I/P) = 10 kHz 30
Medium Mode 50
Slow Mode 65
VIO Offset voltage, I/P 2.2 V, 3 V ±10 mV
Offset temperature drift, I/P See (3) 2.2 V, 3 V ±10 µV/°C
Offset voltage drift with supply, I/P 0.3 V ≤ VIN ≤ VCC – 0.3 V
ΔVCC ≤ ±10%, TA = 25°C
2.2 V, 3 V ±1.5 mV/V
VOH High-level output voltage, O/P Fast Mode, ISOURCE ≤ –500 µA 2.2 V VCC – 0.2 VCC V
Slow Mode, ISOURCE ≤ –150 µA 3 V VCC – 0.1 VCC
VOL Low-level output voltage, O/P Fast Mode, ISOURCE ≤ +500 µA 2.2 V VSS 0.2 V
Slow Mode, ISOURCE ≤ +150 µA 3 V VSS 0.1
RO/P (OAx) Output resistance(4) (see Figure 5-29) RLoad = 3 kΩ,CLoad = 50 pF, RRIP ON,
VO/P(OAx) < 0.2 V
2.2 V, 3 V 150 250 Ω
RLoad = 3 kΩ,CLoad = 50 pF, RRIP ON,
VO/P(OAx) > AVCC – 0.2 V
150 250
RLoad = 3 kΩ,CLoad = 50 pF, RRIP ON,
0.2 V ≤ VO/P(OAx) ≤ AVCC – 0.2 V
0.1 4
CMRR Common-mode rejection ratio Non-inverting 2.2 V, 3 V 70 dB
(1) ESD damage can degrade input current leakage.
(2) The input bias current is overridden by the input leakage current.
(3) Calculated using the box method.
(4) Specification valid for voltage-follower OAx configuration.
slas508_OAx_out_resis.gifFigure 5-29 OAx Output Resistance Tests

5.36 Operational Amplifier (OA), Dynamic Specifications

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SR Slew rate Fast Mode 1.2 V/µs
Medium Mode 0.8
Slow Mode 0.3
Open-loop voltage gain 100 dB
φm Phase margin CL = 50 pF 60 deg
Gain margin CL = 50 pF 20 dB
GBW Gain-bandwidth product
(see Figure 5-30 and Figure 5-31)
Non-inverting, Fast Mode,
RL = 47 kΩ,CL = 50 pF
2.2 V, 3 V 2.2 MHz
1.4
Non-inverting, Medium Mode,
RL = 300 kΩ, CL = 50 pF
0.5
Non-inverting, Slow Mode,
RL = 300 kΩ, CL = 50 pF
ten(on) Enable time on ton, non-inverting, Gain = 1 2.2 V, 3 V 10 20 µs
ten(off) Enable time off 2.2 V, 3 V 1 µs

5.37 OA Dynamic Specifications Typical Characteristics

slas508_graph9.gifFigure 5-30 Typical Open-Loop Gain vs Frequency
slas508_graph10.gifFigure 5-31 Typical Phase vs Frequency

5.38 Flash Memory

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VCC(PGM/ ERASE) Program and erase supply voltage 2.7 3.6 V
fFTG Flash timing generator frequency 257 476 kHz
IPGM Supply current from DVCC during program 2.7 V, 3.6 V 3 5 mA
IERASE Supply current from DVCC during erase 2.7 V, 3.6 V 3 7 mA
tCPT Cumulative program time See  (1)  2.7 V, 3.6 V 10 ms
tCMErase Cumulative mass erase time See  (2)  2.7 V, 3.6 V 200 ms
Program and erase endurance 104 105 cycles
tRetention Data retention duration TJ = 25°C 100 years
tWord Word or byte program time See (3) 35 tFTG
tBlock, 0 Block program time for first byte or word 30
tBlock, 1-63 Block program time for each additional byte or word 21
tBlock, End Block program end-sequence wait time 6
tMass Erase Mass erase time 5297
tSeg Erase Segment erase time 4819
(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word or byte write and block write modes.
(2) The mass erase duration generated by the flash timing generator is at least 11.1 ms ( = 5297 × 1/fFTG,max = 5297 × 1 / 476 kHz). To achieve the required cumulative mass erase time the Flash Controller's mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles are required).
(3) These values are hard-wired into the flash controller's state machine (tFTG = 1 / fFTG).

5.39 JTAG Interface

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fTCK TCK input frequency See (1) 2.2 V 0 5 MHz
3 V 0 10 MHz
RInternal Internal pullup resistance on TMS, TCK, TDI/TCLK See (2) 2.2 V, 3 V 25 60 90
(1) fTCK may be restricted to meet the timing requirements of the module selected.
(2) TMS, TDI/TCLK, and TCK pullup resistors are implemented in all versions.

5.40 JTAG Fuse(1)

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V
VFB Voltage level on TDI/TCLK for fuse-blow 6 7 V
IFB Supply current into TDI/TCLK during fuse blow 100 mA
tFB Time to blow fuse 1 ms
(1) After the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode.