SLAS380D April   2004  – November 2014 MSP430FG437 , MSP430FG438 , MSP430FG439

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3 Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Handling Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Supply Current Into AVCC + DVCC Excluding External Current
    5. 5.5  Schmitt-Trigger Inputs - Ports P1 to P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
    6. 5.6  Inputs Px.y, TAx, TBx
    7. 5.7  Leakage Current - Ports P1 to P6
    8. 5.8  Outputs - Ports P1 to P6
    9. 5.9  Output Frequency
    10. 5.10 Typical Characteristics - Outputs
    11. 5.11 Wake-Up From LPM3
    12. 5.12 RAM
    13. 5.13 LCD
    14. 5.14 Comparator_A
    15. 5.15 Comparator_A Typical Characteristics
    16. 5.16 Power-On Reset (POR) and Brownout Reset (BOR)
    17. 5.17 Supply Voltage Supervisor (SVS) and Supply Voltage Monitor (SVM)
    18. 5.18 DCO
    19. 5.19 Crystal Oscillator, XT1 Oscillator
    20. 5.20 Crystal Oscillator, XT2 Oscillator
    21. 5.21 USART0
    22. 5.22 12-Bit ADC, Power Supply and Input Range Conditions
    23. 5.23 12-Bit ADC, External Reference
    24. 5.24 12-Bit ADC, Built-In Reference
    25. 5.25 12-Bit ADC, Timing Parameters
    26. 5.26 12-Bit ADC, Linearity Parameters
    27. 5.27 12-Bit ADC, Temperature Sensor and Built-In VMID
    28. 5.28 12-Bit DAC, Supply Specifications
    29. 5.29 12-Bit DAC, Linearity Specifications
    30. 5.30 12-Bit DAC, Output Specifications
    31. 5.31 12-Bit DAC, Reference Input Specifications
    32. 5.32 12-Bit DAC, Dynamic Specifications
    33. 5.33 12-Bit DAC, Dynamic Specifications (Continued)
    34. 5.34 Operational Amplifier (OA), Supply Specifications
    35. 5.35 Operational Amplifier (OA), Input/Output Specifications
    36. 5.36 Operational Amplifier (OA), Dynamic Specifications
    37. 5.37 OA Dynamic Specifications Typical Characteristics
    38. 5.38 Flash Memory
    39. 5.39 JTAG Interface
    40. 5.40 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers (SFRs)
      1. 6.5.1 Interrupt Enable Registers 1 and 2
      2. 6.5.2 Interrupt Flag Registers 1 and 2
      3. 6.5.3 Module Enable Registers 1 and 2
    6. 6.6  Memory Organization
    7. 6.7  Bootstrap Loader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
      1. 6.9.1  DMA Controller
      2. 6.9.2  Oscillator and System Clock
      3. 6.9.3  Brownout, Supply Voltage Supervisor
      4. 6.9.4  Digital I/O
      5. 6.9.5  Basic Timer1
      6. 6.9.6  LCD Drive
      7. 6.9.7  OA
      8. 6.9.8  Watchdog Timer (WDT)
      9. 6.9.9  USART0
      10. 6.9.10 Timer_A3
      11. 6.9.11 Timer_B3
      12. 6.9.12 Comparator_A
      13. 6.9.13 ADC12
      14. 6.9.14 DAC12
      15. 6.9.15 Peripheral File Map
    10. 6.10 Input/Output Schematics
      1. 6.10.1  Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger
      2. 6.10.2  Port P1, P1.6 and P1.7, Input/Output With Schmitt Trigger
      3. 6.10.3  Port P2, P2.0 and P2.4 to P2.5, Input/Output With Schmitt Trigger
      4. 6.10.4  Port P2, P2.1 to P2.3, Input/Output With Schmitt Trigger
      5. 6.10.5  Port P2, P2.6 and P2.7, Input/Output With Schmitt Trigger
      6. 6.10.6  Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger
      7. 6.10.7  Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger
      8. 6.10.8  Port P4, P4.0 to P4.5, Input/Output With Schmitt Trigger
      9. 6.10.9  Port P4, P4.6, Input/Output With Schmitt Trigger
      10. 6.10.10 Port P4, P4.7, Input/Output With Schmitt Trigger
      11. 6.10.11 Port P5, P5.0, Input/Output With Schmitt Trigger
      12. 6.10.12 Port P5, P5.1, Input/Output With Schmitt Trigger
      13. 6.10.13 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger
      14. 6.10.14 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger
      15. 6.10.15 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger
      16. 6.10.16 Port P6, P6.1, Input/Output With Schmitt Trigger
      17. 6.10.17 Port P6, P6.3, Input/Output With Schmitt Trigger
      18. 6.10.18 Port P6, P6.5, Input/Output With Schmitt Trigger
      19. 6.10.19 Port P6, P6.6, Input/Output With Schmitt Trigger
      20. 6.10.20 Port P6, P6.7, Input/Output With Schmitt Trigger
      21. 6.10.21 VeREF+/DAC0
      22. 6.10.22 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output
      23. 6.10.23 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
        1. 7.1.1.1 Development Kit
      2. 7.1.2 Device and Development Tool Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Related Links
      2. 7.2.2 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the pin assignments for the 80-pin PN package.

pinout_pn80_slas380.gifFigure 4-1 80-Pin PN Package (Top View)

Figure 4-2 shows the pin assignments for the 113-pin ZCA package.

pinout_zca113_slas380.gifFigure 4-2 113-Pin ZCA Package (Top View)

4.2 Signal Descriptions

Table 4-1 describes the signals for all device variants and package options.

Table 4-1 Signal Descriptions

TERMINAL I/O DESCRIPTION
NAME NO.
PN ZCA
DVCC1 1 B1, C2 Digital supply voltage, positive terminal.
P6.3/A3/OA1I1/OA1O 2 B5 I/O General-purpose digital I/O
Analog input a3—12-bit ADC
OA1 output and/or input multiplexer on +terminal and −terminal
P6.4/A4/OA1I0 3 D5 I/O General-purpose digital I/O
Analog input a4—12-bit ADC
OA1 input multiplexer on +terminal and −terminal
P6.5/A5/OA2I1/OA2O 4 D4 I/O General-purpose digital I/O
Analog input a5—12-bit ADC
OA2 output and/or input multiplexer on +terminal and −terminal
P6.6/A6/DAC0/OA2I0 5 E4 I/O General-purpose digital I/O
Analog input a6—12-bit ADC
DAC12.0 output
OA2 input multiplexer on +terminal and −terminal
P6.7/A7/DAC1/SVSIN 6 D2 I/O General-purpose digital I/O
Analog input a7—12-bit ADC
DAC12.1 output/analog input to supply voltage supervisor
VREF+ 7 C1 O Positive output terminal of the reference voltage in the ADC
XIN 8 E1 I Input terminal of crystal oscillator XT1
XOUT 9 F1 O Output terminal of crystal oscillator XT1
VeREF+/DAC0 10 H1 I/O Positive input terminal for an external reference voltage to the 12-bit ADC/DAC12.0 output
VREF−/VeREF− 11 J1 I Negative terminal for the 12-bit ADC's reference voltage for both sources, the internal reference voltage or an external applied reference voltage to the 12-bit ADC.
P5.1/S0/A12/DAC1 12 F4 I/O General-purpose digital I/O
LCD segment output 0
Analog input a12—12-bit ADC
DAC12.1 output
P5.0/S1/A13 13 G4 I/O General-purpose digital I/O
LCD segment output 1
Analog input a13—12-bit ADC
P4.7/S2/A14 14 H4 I/O General-purpose digital I/O
LCD segment output 2
Analog input a14—12-bit ADC
P4.6/S3/A15 15 J4 I/O General-purpose digital I/O
LCD segment output 3
Analog input a15—12-bit ADC
P4.5/S4 16 K1 I/O General-purpose digital I/O
LCD segment output 4
P4.4/S5 17 K2 I/O General-purpose digital I/O
LCD segment output 5
P4.3/S6 18 L3 I/O General-purpose digital I/O
LCD segment output 6
P4.2/S7 19 L2 I/O General-purpose digital I/O
LCD segment output 7
P4.1/S8 20 L1 I/O General-purpose digital I/O
LCD segment output 8
P4.0/S9 21 M2 I/O General-purpose digital I/O
LCD segment output 9
S10 22 M3 O LCD segment output 10
S11 23 L4 O LCD segment output 11
S12 24 M4 O LCD segment output 12
S13 25 J5 O LCD segment output 13
S14 26 L5 O LCD segment output 14
S15 27 M5 O LCD segment output 15
S16 28 J6 O LCD segment output 16
S17 29 L6 O LCD segment output 17
P2.7/ADC12CLK/S18 30 M6 I/O General-purpose digital I/O
Conversion clock—12-bit ADC
LCD segment output 18
P2.6/CAOUT/S19 31 M7 I/O General-purpose digital I/O
Comparator_A output / LCD segment output 19
S20 32 L7 O LCD segment output 20
S21 33 J7 O LCD segment output 21
S22 34 J8 O LCD segment output 22
S23 35 J9 O LCD segment output 23
P3.7/S24 36 M8 I/O General-purpose digital I/O
LCD segment output 24
P3.6/S25/DMAE0 37 L8 I/O General-purpose digital I/O
LCD segment output 25/DMA Channel 0 external trigger
P3.5/S26 38 L9 I/O General-purpose digital I/O
LCD segment output 26
P3.4/S27 39 L10 I/O General-purpose digital I/O
LCD segment output 27
P3.3/UCLK0/S28 40 M9 I/O General-purpose digital I/O
External clock input—USART0/UART or SPI mode, clock output—USART0/SPI mode
LCD segment output 28
P3.2/SOMI0/S29 41 M10 I/O General-purpose digital I/O
Slave out/master in of USART0/SPI mode
LCD segment output 29
P3.1/SIMO0/S30 42 M11 I/O General-purpose digital I/O
Slave in/master out of USART0/SPI mode
LCD segment output 30
P3.0/STE0/S31 43 L12 I/O General-purpose digital I/O
Slave transmit enable-USART0/SPI mode
LCD segment output 31
COM0 44 K11 O Common output, COM0−3 are used for LCD backplanes.
P5.2/COM1 45 J11 I/O General-purpose digital I/O
Common output, COM0−3 are used for LCD backplanes.
P5.3/COM2 46 H11 I/O General-purpose digital I/O
Common output, COM0−3 are used for LCD backplanes.
P5.4/COM3 47 G11 I/O General-purpose digital I/O
Common output, COM0−3 are used for LCD backplanes.
R03 48 K12 I Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13 49 J12 I/O General-purpose digital I/O
input port of third most positive analog LCD level (V4 or V3)
P5.6/R23 50 H12 I/O General-purpose digital I/O
Input port of second most positive analog LCD level (V2)
P5.7/R33 51 G12 I/O General-purpose digital I/O
Output port of most positive analog LCD level (V1)
DVCC2 52 F12 Digital supply voltage, positive terminal
DVSS2 53 E12 Digital supply voltage, negative terminal
P2.5/URXD0 54 D12 I/O General-purpose digital I/O
Receive data in—USART0/UART mode
P2.4/UTXD0 55 C12 I/O General-purpose digital I/O
Transmit data out—USART0/UART mode
P2.3/TB2 56 F11 I/O General-purpose digital I/O
Timer_B3 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1 57 E11 I/O General-purpose digital I/O
Timer_B3 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0 58 D11 I/O General-purpose digital I/O
Timer_B3 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2 59 C11 I/O General-purpose digital I/O
Timer_A Capture: CCI2A input, compare: Out2 output
P1.7/CA1 60 B12 I/O General-purpose digital I/O
Comparator_A input
P1.6/CA0 61 A11 I/O General-purpose digital I/O
Comparator_A input
P1.5/TACLK/ACLK 62 B10 I/O General-purpose digital I/O
Timer_A, clock signal TACLK input
ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/SMCLK 63 E9 I/O General-purpose digital I/O
Input clock TBCLK—Timer_B3
Submain system clock SMCLK output
P1.3/TBOUTH/SVSOUT 64 A10 I/O General-purpose digital I/O
Switch all PWM digital output ports to high impedance—Timer_B3 TB0 to TB2
SVS: output of SVS comparator
P1.2/TA1 65 B9 I/O General-purpose digital I/O
Timer_A, Capture: CCI1A, compare: Out1 output
P1.1/TA0/MCLK 66 D9 I/O General-purpose digital I/O
Timer_A. Capture: CCI0B / MCLK output. Note: TA0 is only an input on this pin
BSL receive
P1.0/TA0 67 D8 I/O General-purpose digital I/O
Timer_A. Capture: CCI0A input, compare: Out0 output
BSL transmit
XT2OUT 68 A8 O Output terminal of crystal oscillator XT2
XT2IN 69 A7 I Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI 70 D7 I/O Test data output port. TDO/TDI data output or programming data input terminal
TDI/TCLK 71 E7 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS 72 D6 I Test mode select. TMS is used as an input port for device programming and test.
TCK 73 E6 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 74 A6 I Reset or nonmaskable interrupt input
P6.0/A0/OA0I0 75 A5 I/O General-purpose digital I/O
Analog input a0 − 12-bit ADC
OA0 input multiplexer on +terminal and −terminal
P6.1/A1/OA0O 76 A4 I/O General-purpose digital I/O
Analog input a1 − 12-bit ADC
OA0 output
P6.2/A2/OA0I1 77 B4 I/O General-purpose digital I/O
Analog input a2 − 12-bit ADC
OA0 input multiplexer on + terminal and − terminal
AVSS 78 A2, D1, E2, F2, G2, G1, H2, J2 Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1, and LCD resistive divider circuitry.
DVSS1 79 A1, B2, C3, B6, B7, B8, A9 Digital supply voltage, negative terminal
AVCC 80 A3, B3 Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1, and LCD resistive divider circuitry; must not power up prior to DVCC1/DVCC2.
Reserved  (1) Reserved
(1) A12, B11, E5, E8, F5, F8, F9, G5, G8, G9, H5, H6, H7, H8, H9, L11, M1, M12 are reserved and should be connected to ground.