SLASEC4D May   2018  – December 2019 MSP430FR2153 , MSP430FR2155 , MSP430FR2353 , MSP430FR2355

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
      1.      Revision History
  2. 2Device Comparison
    1. 2.1 Related Products
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagrams
    2. 3.2 Pin Attributes
    3. 3.3 Signal Descriptions
    4. 3.4 Pin Multiplexing
    5. 3.5 Buffer Type
    6. 3.6 Connection of Unused Pins
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 4.5  Active Mode Supply Current Per MHz
    6. 4.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 4.7  Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 4.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 4.9  Production Distribution of LPM Supply Currents
    10. 4.10 Typical Characteristics - Current Consumption Per Module
    11. 4.11 Thermal Resistance Characteristics
    12. 4.12 Timing and Switching Characteristics
      1. 4.12.1  Power Supply Sequencing
        1. Table 4-1 PMM, SVS and BOR
      2. 4.12.2  Reset Timing
        1. Table 4-2 Wake-up Times From Low-Power Modes and Reset
      3. 4.12.3  Clock Specifications
        1. Table 4-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 4-4 XT1 Crystal Oscillator (High Frequency)
        3. Table 4-5 DCO FLL, Frequency
        4. Table 4-6 DCO Frequency
        5. Table 4-7 REFO
        6. Table 4-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        7. Table 4-9 Module Oscillator (MODOSC)
      4. 4.12.4  Internal Shared Reference
        1. Table 4-10 Internal Shared Reference
      5. 4.12.5  General-Purpose I/Os
        1. Table 4-11 Digital Inputs
        2. Table 4-12 Digital Outputs
      6. 4.12.6  Digital I/O Typical Characteristics
      7. 4.12.7  Timer_B
        1. Table 4-13 Timer_B
      8. 4.12.8  eUSCI
        1. Table 4-14 eUSCI (UART Mode) Clock Frequencies
        2. Table 4-15 eUSCI (UART Mode) Switching Characteristics
        3. Table 4-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 4-17 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 4-18 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 4-19 eUSCI (I2C Mode) Switching Characteristics
      9. 4.12.9  ADC
        1. Table 4-20 ADC, Power Supply and Input Range Conditions
        2. Table 4-21 ADC, Timing Parameters
        3. Table 4-22 ADC, Linearity Parameters
      10. 4.12.10 Enhanced Comparator (eCOMP)
        1. Table 4-23 eCOMP0
        2. Table 4-24 eCOMP1
      11. 4.12.11 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
        1. Table 4-25 SAC, OA
        2. Table 4-26 SAC, DAC
      12. 4.12.12 FRAM
        1. Table 4-27 FRAM
      13. 4.12.13 Emulation and Debug
        1. Table 4-28 JTAG, Spy-Bi-Wire Interface
        2. Table 4-29 JTAG, 4-Wire Interface
  5. 5Detailed Description
    1. 5.1  CPU
    2. 5.2  Operating Modes
    3. 5.3  Interrupt Vector Addresses
    4. 5.4  Memory Organization
    5. 5.5  Bootloader (BSL)
    6. 5.6  JTAG Standard Interface
    7. 5.7  Spy-Bi-Wire Interface (SBW)
    8. 5.8  FRAM
    9. 5.9  Memory Protection
    10. 5.10 Peripherals
      1. 5.10.1  Power Management Module (PMM) and On-Chip Reference Voltages
      2. 5.10.2  Clock System (CS) and Clock Distribution
      3. 5.10.3  General-Purpose Input/Output Port (I/O)
      4. 5.10.4  Watchdog Timer (WDT)
      5. 5.10.5  System Module (SYS)
      6. 5.10.6  Cyclic Redundancy Check (CRC)
      7. 5.10.7  Interrupt Compare Controller (ICC)
      8. 5.10.8  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_A1, eUSCI_B0, eUSCI_B1)
      9. 5.10.9  Timers (Timer0_B3, Timer1_B3, Timer2_B3, Timer3_B7)
      10. 5.10.10 Backup Memory (BKMEM)
      11. 5.10.11 Real-Time Clock (RTC) Counter
      12. 5.10.12 12-Bit Analog-to-Digital Converter (ADC)
      13. 5.10.13 Enhanced Comparator
      14. 5.10.14 Manchester Function Module (MFM)
      15. 5.10.15 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
      16. 5.10.16 eCOMP0, eCOMP1, SAC0, SAC1, SAC2, and SAC3 Interconnection (MSP430FR235x Devices Only)
      17. 5.10.17 Cross-Chip Interconnection (SACx are MSP430FR235x Devices Only)
      18. 5.10.18 Embedded Emulation Module (EEM)
      19. 5.10.19 Peripheral File Map
    11. 5.11 Input/Output Diagrams
      1. 5.11.1 Port P1 Input/Output With Schmitt Trigger
      2. 5.11.2 Port P2 Input/Output With Schmitt Trigger
      3. 5.11.3 Port P3 Input/Output With Schmitt Trigger
      4. 5.11.4 Port P4 Input/Output With Schmitt Trigger
      5. 5.11.5 Port P5 Input/Output With Schmitt Trigger
      6. 5.11.6 Port P6 Input/Output With Schmitt Trigger
    12. 5.12 Device Descriptors (TLV)
    13. 5.13 Identification
      1. 5.13.1 Revision Identification
      2. 5.13.2 Device Identification
      3. 5.13.3 JTAG Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Device Connection and Layout Fundamentals
      1. 6.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 6.1.2 External Oscillator
      3. 6.1.3 JTAG
      4. 6.1.4 Reset
      5. 6.1.5 Unused Pins
      6. 6.1.6 General Layout Recommendations
      7. 6.1.7 Do's and Don'ts
    2. 6.2 Peripheral- and Interface-Specific Design Information
      1. 6.2.1 ADC Peripheral
        1. 6.2.1.1 Partial Schematic
        2. 6.2.1.2 Design Requirements
        3. 6.2.1.3 Layout Guidelines
    3. 6.3 ROM Libraries
    4. 6.4 Typical Applications
  7. 7Device and Documentation Support
    1. 7.1 Getting Started
    2. 7.2 Device Nomenclature
    3. 7.3 Tools and Software
    4. 7.4 Documentation Support
    5. 7.5 Related Links
    6. 7.6 Trademarks
    7. 7.7 Electrostatic Discharge Caution
    8. 7.8 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Peripheral File Map

Table 5-33 lists the base address and the memory size of each peripheral's registers.

Table 5-33 Peripherals Summary

MODULE NAME BASE ADDRESS SIZE
Special Functions (see Table 5-34) 0100h 0010h
PMM (see Table 5-35) 0120h 0020h
SYS (see Table 5-36) 0140h 0040h
CS (see Table 5-37) 0180h 0020h
FRAM (see Table 5-38) 01A0h 0010h
CRC (see Table 5-39) 01C0h 0008h
WDT (see Table 5-40) 01CCh 0002h
Port P1, P2 (see Table 5-41) 0200h 0020h
Port P3, P4 (see Table 5-42) 0220h 0020h
Port P5, P6 (see Table 5-43) 0240h 0020h
RTC (see Table 5-44) 0300h 0010h
Timer0_B3 (see Table 5-45) 0380h 0030h
Timer1_B3 (see Table 5-46) 03C0h 0030h
Timer2_B3 (see Table 5-47) 0400h 0030h
Timer3_B7 (see Table 5-48) 0440h 0030h
MPY32 (see Table 5-49) 04C0h 0030h
eUSCI_A0 (see Table 5-50) 0500h 0020h
eUSCI_B0 (see Table 5-51) 0540h 0030h
eUSCI_A1 (see Table 5-52) 0580h 0020h
eUSCI_B1 (see Table 5-53) 05C0h 0030h
Backup Memory (see Table 5-54) 0660h 0020h
ICC (see Table 5-55) 06C0h 0010h
ADC (see Table 5-56) 0700h 0040h
eCOMP0 (see Table 5-57) 08E0h 0020h
eCOMP1 (see Table 5-58) 0900h 0020h
SAC0 (see Table 5-59)(1) 0C80h 0010h
SAC1 (see Table 5-60)(1) 0C90h 0010h
SAC2 (see Table 5-61)(1) 0CA0h 0010h
SAC3 (see Table 5-62)(1) 0CB0h 0010h
MSP430FR235x devices only

Table 5-34 Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION ACRONYM OFFSET
SFR interrupt enable SFRIE1 00h
SFR interrupt flag SFRIFG1 02h
SFR reset pin control SFRRPCR 04h

Table 5-35 PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION ACRONYM OFFSET
PMM control 0 PMMCTL0 00h
PMM control 1 PMMCTL1 02h
PMM control 2 PMMCTL2 04h
PMM interrupt flags PMMIFG 0Ah
PM5 control 0 PM5CTL0 10h

Table 5-36 SYS Registers (Base Address: 0140h)

REGISTER DESCRIPTION ACRONYM OFFSET
System control SYSCTL 00h
Bootloader configuration area SYSBSLC 02h
JTAG mailbox control SYSJMBC 06h
JTAG mailbox input 0 SYSJMBI0 08h
JTAG mailbox input 1 SYSJMBI1 0Ah
JTAG mailbox output 0 SYSJMBO0 0Ch
JTAG mailbox output 1 SYSJMBO1 0Eh
User NMI vector generator SYSUNIV 1Ah
System NMI vector generator SYSSNIV 1Ch
Reset vector generator SYSRSTIV 1Eh
System configuration 0 SYSCFG0 20h
System configuration 1 SYSCFG1 22h
System configuration 2 SYSCFG2 24h
System configuration 3 SYSCFG3 26h

Table 5-37 CS Registers (Base Address: 0180h)

REGISTER DESCRIPTION ACRONYM OFFSET
CS control 0 CSCTL0 00h
CS control 1 CSCTL1 02h
CS control 2 CSCTL2 04h
CS control 3 CSCTL3 06h
CS control 4 CSCTL4 08h
CS control 5 CSCTL5 0Ah
CS control 6 CSCTL6 0Ch
CS control 7 CSCTL7 0Eh
CS control 8 CSCTL8 10h

Table 5-38 FRAM Registers (Base Address: 01A0h)

REGISTER DESCRIPTION ACRONYM OFFSET
FRAM control 0 FRCTL0 00h
General control 0 GCCTL0 04h
General control 1 GCCTL1 06h

Table 5-39 CRC Registers (Base Address: 01C0h)

REGISTER DESCRIPTION ACRONYM OFFSET
CRC data input CRC16DI 00h
CRC data input reverse byte CRCDIRB 02h
CRC initialization and result CRCINIRES 04h
CRC result reverse byte CRCRESR 06h

Table 5-40 WDT Registers (Base Address: 01CCh)

REGISTER DESCRIPTION ACRONYM OFFSET
Watchdog timer control WDTCTL 00h

Table 5-41 Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION ACRONYM OFFSET
Port P1 input P1IN 00h
Port P1 output P1OUT 02h
Port P1 direction P1DIR 04h
Port P1 pulling enable P1REN 06h
Port P1 selection 0 P1SEL0 0Ah
Port P1 selection 1 P1SEL1 0Ch
Port P1 interrupt vector word P1IV 0Eh
Port P1 complement selection P1SELC 16h
Port P1 interrupt edge select P1IES 18h
Port P1 interrupt enable P1IE 1Ah
Port P1 interrupt flag P1IFG 1Ch
Port P2 input P2IN 01h
Port P2 output P2OUT 03h
Port P2 direction P2DIR 05h
Port P2 pulling enable P2REN 07h
Port P2 selection 0 P2SEL0 0Bh
Port P2 selection 1 P2SEL1 0Dh
Port P2 interrupt vector word P2IV 1Eh
Port P2 complement selection P2SELC 17h
Port P2 interrupt edge select P2IES 19h
Port P2 interrupt enable P2IE 1Bh
Port P2 interrupt flag P2IFG 1Dh

Table 5-42 Port P3, P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION ACRONYM OFFSET
Port P3 input P3IN 00h
Port P3 output P3OUT 02h
Port P3 direction P3DIR 04h
Port P3 pulling enable P3REN 06h
Port P3 selection 0 P3SEL0 0Ah
Port P3 selection 1 P3SEL1 0Ch
Port P3 interrupt vector word P3IV 0Eh
Port P3 complement selection P3SELC 16h
Port P3 interrupt edge select P3IES 18h
Port P3 interrupt enable P3IE 1Ah
Port P3 interrupt flag P3IFG 1Ch
Port P4 input P4IN 01h
Port P4 output P4OUT 03h
Port P4 direction P4DIR 05h
Port P4 pulling enable P4REN 07h
Port P4 selection 0 P4SEL0 0Bh
Port P4 selection 1 P4SEL1 0Dh
Port P4 interrupt vector word P4IV 1Eh
Port P4 complement selection P4SELC 17h
Port P4 interrupt edge select P4IES 19h
Port P4 interrupt enable P4IE 1Bh
Port P4 interrupt flag P4IFG 1Dh

Table 5-43 Port P5, P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION ACRONYM OFFSET
Port P5 input P5IN 00h
Port P5 output P5OUT 02h
Port P5 direction P5DIR 04h
Port P5 pulling enable P5REN 06h
Port P5 selection 0 P5SEL0 0Ah
Port P5 selection 1 P5SEL1 0Ch
Port P5 complement selection P5SELC 16h
Port P6 input P6IN 01h
Port P6 output P6OUT 03h
Port P6 direction P6DIR 05h
Port P6 pulling enable P6REN 07h
Port P6 selection 0 P6SEL0 0Bh
Port P6 selection 1 P6SEL1 0Dh
Port P6 complement selection P6SELC 17h

Table 5-44 RTC Registers (Base Address: 0300h)

REGISTER DESCRIPTION ACRONYM OFFSET
RTC control RTCCTL 00h
RTC interrupt vector RTCIV 04h
RTC modulo RTCMOD 08h
RTC counter RTCCNT 0Ch

Table 5-45 Timer0_B3 Registers (Base Address: 0380h)

REGISTER DESCRIPTION ACRONYM OFFSET
TB0 control TB0CTL 00h
Capture/compare control 0 TB0CCTL0 02h
Capture/compare control 1 TB0CCTL1 04h
Capture/compare control 2 TB0CCTL2 06h
TB0 counter TB0R 10h
Capture/compare 0 TB0CCR0 12h
Capture/compare 1 TB0CCR1 14h
Capture/compare 2 TB0CCR2 16h
TB0 expansion 0 TB0EX0 20h
TB0 interrupt vector TB0IV 2Eh

Table 5-46 Timer1_B3 Registers (Base Address: 03C0h)

REGISTER DESCRIPTION ACRONYM OFFSET
TB1 control TB1CTL 00h
Capture/compare control 0 TB1CCTL0 02h
Capture/compare control 1 TB1CCTL1 04h
Capture/compare control 2 TB1CCTL2 06h
TB1 counter TB1R 10h
Capture/compare 0 TB1CCR0 12h
Capture/compare 1 TB1CCR1 14h
Capture/compare 2 TB1CCR2 16h
TB1 expansion 0 TB1EX0 20h
TB1 interrupt vector TB1IV 2Eh

Table 5-47 Timer2_B3 Registers (Base Address: 0400h)

REGISTER DESCRIPTION ACRONYM OFFSET
TB2 control TB2CTL 00h
Capture/compare control 0 TB2CCTL0 02h
Capture/compare control 1 TB2CCTL1 04h
Capture/compare control 2 TB2CCTL2 06h
TB2 counter TB2R 10h
Capture/compare 0 TB2CCR0 12h
Capture/compare 1 TB2CCR1 14h
Capture/compare 2 TB2CCR2 16h
TB2 expansion 0 TB2EX0 20h
TB2 interrupt vector TB2IV 2Eh

Table 5-48 Timer3_B7 Registers (Base Address: 0440h)

REGISTER DESCRIPTION ACRONYM OFFSET
TB3 control TB3CTL 00h
Capture/compare control 0 TB3CCTL0 02h
Capture/compare control 1 TB3CCTL1 04h
Capture/compare control 2 TB3CCTL2 06h
Capture/compare control 3 TB3CCTL3 08h
Capture/compare control 4 TB3CCTL4 0Ah
Capture/compare control 5 TB3CCTL5 0Ch
Capture/compare control 6 TB3CCTL6 0Eh
TB3 counter TB3R 10h
Capture/compare 0 TB3CCR0 12h
Capture/compare 1 TB3CCR1 14h
Capture/compare 2 TB3CCR2 16h
Capture/compare 3 TB3CCR3 18h
Capture/compare 4 TB3CCR4 1Ah
Capture/compare 5 TB3CCR5 1Ch
Capture/compare 6 TB3CCR6 1Eh
TB3 expansion 0 TB3EX0 20h
TB3 interrupt vector TB3IV 2Eh

Table 5-49 MPY32 Registers (Base Address: 04C0h)

REGISTER DESCRIPTION ACRONYM OFFSET
16-bit operand 1 – multiply MPY 00h
16-bit operand 1 – signed multiply MPYS 02h
16-bit operand 1 – multiply accumulate MAC 04h
16-bit operand 1 – signed multiply accumulate MACS 06h
16-bit operand 2 OP2 08h
16 × 16 result low word RESLO 0Ah
16 × 16 result high word RESHI 0Ch
16 × 16 sum extension SUMEXT 0Eh
32-bit operand 1 – multiply low word MPY32L 10h
32-bit operand 1 – multiply high word MPY32H 12h
32-bit operand 1 – signed multiply low word MPYS32L 14h
32-bit operand 1 – signed multiply high word MPYS32H 16h
32-bit operand 1 – multiply accumulate low word MAC32L 18h
32-bit operand 1 – multiply accumulate high word MAC32H 1Ah
32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch
32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh
32-bit operand 2 – low word OP2L 20h
32-bit operand 2 – high word OP2H 22h
32 × 32 result 0 – least significant word RES0 24h
32 × 32 result 1 RES1 26h
32 × 32 result 2 RES2 28h
32 × 32 result 3 – most significant word RES3 2Ah
MPY32 control 0 MPY32CTL0 2Ch

Table 5-50 eUSCI_A0 Registers (Base Address: 0500h)

REGISTER DESCRIPTION ACRONYM OFFSET
eUSCI_A control word 0 UCA0CTLW0 00h
eUSCI_A control word 1 UCA0CTLW1 02h
eUSCI_A control rate 0 UCA0BR0 06h
eUSCI_A control rate 1 UCA0BR1 07h
eUSCI_A modulation control UCA0MCTLW 08h
eUSCI_A status UCA0STAT 0Ah
eUSCI_A receive buffer UCA0RXBUF 0Ch
eUSCI_A transmit buffer UCA0TXBUF 0Eh
eUSCI_A LIN control UCA0ABCTL 10h
eUSCI_A IrDA transmit control lUCA0IRTCTL 12h
eUSCI_A IrDA receive control IUCA0IRRCTL 13h
eUSCI_A interrupt enable UCA0IE 1Ah
eUSCI_A interrupt flags UCA0IFG 1Ch
eUSCI_A interrupt vector word UCA0IV 1Eh

Table 5-51 eUSCI_B0 Registers (Base Address: 0540h)

REGISTER DESCRIPTION ACRONYM OFFSET
eUSCI_B control word 0 UCB0CTLW0 00h
eUSCI_B control word 1 UCB0CTLW1 02h
eUSCI_B bit rate 0 UCB0BR0 06h
eUSCI_B bit rate 1 UCB0BR1 07h
eUSCI_B status word UCB0STATW 08h
eUSCI_B byte counter threshold UCB0TBCNT 0Ah
eUSCI_B receive buffer UCB0RXBUF 0Ch
eUSCI_B transmit buffer UCB0TXBUF 0Eh
eUSCI_B I2C own address 0 UCB0I2COA0 14h
eUSCI_B I2C own address 1 UCB0I2COA1 16h
eUSCI_B I2C own address 2 UCB0I2COA2 18h
eUSCI_B I2C own address 3 UCB0I2COA3 1Ah
eUSCI_B receive address UCB0ADDRX 1Ch
eUSCI_B address mask UCB0ADDMASK 1Eh
eUSCI_B I2C slave address UCB0I2CSA 20h
eUSCI_B interrupt enable UCB0IE 2Ah
eUSCI_B interrupt flags UCB0IFG 2Ch
eUSCI_B interrupt vector word UCB0IV 2Eh

Table 5-52 eUSCI_A1 Registers (Base Address: 0580h)

REGISTER DESCRIPTION ACRONYM OFFSET
eUSCI_A control word 0 UCA1CTLW0 00h
eUSCI_A control word 1 UCA1CTLW1 02h
eUSCI_A control rate 0 UCA1BR0 06h
eUSCI_A control rate 1 UCA1BR1 07h
eUSCI_A modulation control UCA1MCTLW 08h
eUSCI_A status UCA1STAT 0Ah
eUSCI_A receive buffer UCA1RXBUF 0Ch
eUSCI_A transmit buffer UCA1TXBUF 0Eh
eUSCI_A LIN control UCA1ABCTL 10h
eUSCI_A IrDA transmit control lUCA1IRTCTL 12h
eUSCI_A IrDA receive control IUCA1IRRCTL 13h
eUSCI_A interrupt enable UCA1IE 1Ah
eUSCI_A interrupt flags UCA1IFG 1Ch
eUSCI_A interrupt vector word UCA1IV 1Eh

Table 5-53 eUSCI_B1 Registers (Base Address: 05C0h)

REGISTER DESCRIPTION ACRONYM OFFSET
eUSCI_B control word 0 UCB1CTLW0 00h
eUSCI_B control word 1 UCB1CTLW1 02h
eUSCI_B bit rate 0 UCB1BR0 06h
eUSCI_B bit rate 1 UCB1BR1 07h
eUSCI_B status word UCB1STATW 08h
eUSCI_B byte counter threshold UCB1TBCNT 0Ah
eUSCI_B receive buffer UCB1RXBUF 0Ch
eUSCI_B transmit buffer UCB1TXBUF 0Eh
eUSCI_B I2C own address 0 UCB1I2COA0 14h
eUSCI_B I2C own address 1 UCB1I2COA1 16h
eUSCI_B I2C own address 2 UCB1I2COA2 18h
eUSCI_B I2C own address 3 UCB1I2COA3 1Ah
eUSCI_B receive address UCB1ADDRX 1Ch
eUSCI_B address mask UCB1ADDMASK 1Eh
eUSCI_B I2C slave address UCB1I2CSA 20h
eUSCI_B interrupt enable UCB1IE 2Ah
eUSCI_B interrupt flags UCB1IFG 2Ch
eUSCI_B interrupt vector word UCB1IV 2Eh

Table 5-54 Backup Memory Registers (Base Address: 0660h)

REGISTER DESCRIPTION ACRONYM OFFSET
Backup memory 0 BAKMEM0 00h
Backup memory 1 BAKMEM1 02h
Backup memory 2 BAKMEM2 04h
Backup memory 3 BAKMEM3 06h
Backup memory 4 BAKMEM4 08h
Backup memory 5 BAKMEM5 0Ah
Backup memory 6 BAKMEM6 0Ch
Backup memory 7 BAKMEM7 0Eh
Backup memory 8 BAKMEM8 10h
Backup memory 9 BAKMEM9 12h
Backup memory 10 BAKMEM10 14h
Backup memory 11 BAKMEM11 16h
Backup memory 12 BAKMEM12 18h
Backup memory 13 BAKMEM13 1Ah
Backup memory 14 BAKMEM14 1Ch
Backup memory 15 BAKMEM15 1Eh

Table 5-55 ICC Registers (Base Address: 06C0h)

REGISTER DESCRIPTION ACRONYM OFFSET
ICC status and control ICCSC 00h
ICC mask virtual stack ICCMVS 02h
ICC interrupt level setting 0 ICCILSR0 04h
ICC interrupt level setting 1 ICCILSR1 06h
ICC interrupt level setting 2 ICCILSR2 08h
ICC interrupt level setting 3 ICCILSR3 0Ah

Table 5-56 ADC Registers (Base Address: 0700h)

REGISTER DESCRIPTION ACRONYM OFFSET
ADC control 0 ADCCTL0 00h
ADC control 1 ADCCTL1 02h
ADC control 2 ADCCTL2 04h
ADC window comparator low threshold ADCLO 06h
ADC window comparator high threshold ADCHI 08h
ADC memory control 0 ADCMCTL0 0Ah
ADC conversion memory ADCMEM0 12h
ADC interrupt enable ADCIE 1Ah
ADC interrupt flags ADCIFG 1Ch
ADC interrupt vector word ADCIV 1Eh

Table 5-57 eCOMP0 Registers (Base Address: 08E0h)

REGISTER DESCRIPTION ACRONYM OFFSET
Comparator control 0 CP0CTL0 00h
Comparator control 1 CP0CTL1 02h
Comparator interrupt CP0INT 06h
Comparator interrupt vector CP0IV 08h
Comparator built-in DAC control CP0DACCTL 10h
Comparator built-in DAC data CP0DACDATA 12h

Table 5-58 eCOMP1 Registers (Base Address: 0900h)

REGISTER DESCRIPTION ACRONYM OFFSET
Comparator control 0 CP1CTL0 00h
Comparator control 1 CP1CTL1 02h
Comparator interrupt CP1INT 06h
Comparator interrupt vector CP1IV 08h
Comparator built-in DAC control CP1DACCTL 10h
Comparator built-in DAC data CP1DACDATA 12h

Table 5-59 SAC0 Registers (Base Address: 0C80h, MSP430FR235x Devices Only)

REGISTER DESCRIPTION ACRONYM OFFSET
SAC0 OA control SAC0OA 00h
SAC0 PGA control SAC0PGA 02h
SAC0 DAC control SAC0DAC 04h
SAC0 DAC data SAC0DAT 06h
SAC0 DAC status SAC0DATSTS 08h
SAC0 interrupt vector SAC0IV 0Ah

Table 5-60 SAC1 Registers (Base Address: 0C90h, MSP430FR235x Devices Only)

REGISTER DESCRIPTION ACRONYM OFFSET
SAC1 OA control SAC1OA 00h
SAC1 PGA control SAC1PGA 02h
SAC1 DAC control SAC1DAC 04h
SAC1 DAC data SAC1DAT 06h
SAC1 DAC status SAC1DATSTS 08h
SAC1 interrupt vector SAC1IV 0Ah

Table 5-61 SAC2 Registers (Base Address: 0CA0h, MSP430FR235x Devices Only)

REGISTER DESCRIPTION ACRONYM OFFSET
SAC2 OA control SAC2OA 00h
SAC2 PGA control SAC2PGA 02h
SAC2 DAC control SAC2DAC 04h
SAC2 DAC data SAC2DAT 06h
SAC2 DAC status SAC2DATSTS 08h
SAC2 interrupt vector SAC2IV 0Ah

Table 5-62 SAC3 Registers (Base Address: 0CB0h, MSP430FR235x Devices Only)

REGISTER DESCRIPTION ACRONYM OFFSET
SAC3 OA control SAC3OA 00h
SAC3 PGA control SAC3PGA 02h
SAC3 DAC control SAC3DAC 04h
SAC3 DAC data SAC3DAT 06h
SAC3 DAC status SAC3DATSTS 08h
SAC3 interrupt vector SAC3IV 0Ah