SLASEC4D May   2018  – December 2019 MSP430FR2153 , MSP430FR2155 , MSP430FR2353 , MSP430FR2355

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
      1.      Revision History
  2. 2Device Comparison
    1. 2.1 Related Products
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagrams
    2. 3.2 Pin Attributes
    3. 3.3 Signal Descriptions
    4. 3.4 Pin Multiplexing
    5. 3.5 Buffer Type
    6. 3.6 Connection of Unused Pins
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 4.5  Active Mode Supply Current Per MHz
    6. 4.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 4.7  Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 4.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 4.9  Production Distribution of LPM Supply Currents
    10. 4.10 Typical Characteristics - Current Consumption Per Module
    11. 4.11 Thermal Resistance Characteristics
    12. 4.12 Timing and Switching Characteristics
      1. 4.12.1  Power Supply Sequencing
        1. Table 4-1 PMM, SVS and BOR
      2. 4.12.2  Reset Timing
        1. Table 4-2 Wake-up Times From Low-Power Modes and Reset
      3. 4.12.3  Clock Specifications
        1. Table 4-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 4-4 XT1 Crystal Oscillator (High Frequency)
        3. Table 4-5 DCO FLL, Frequency
        4. Table 4-6 DCO Frequency
        5. Table 4-7 REFO
        6. Table 4-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        7. Table 4-9 Module Oscillator (MODOSC)
      4. 4.12.4  Internal Shared Reference
        1. Table 4-10 Internal Shared Reference
      5. 4.12.5  General-Purpose I/Os
        1. Table 4-11 Digital Inputs
        2. Table 4-12 Digital Outputs
      6. 4.12.6  Digital I/O Typical Characteristics
      7. 4.12.7  Timer_B
        1. Table 4-13 Timer_B
      8. 4.12.8  eUSCI
        1. Table 4-14 eUSCI (UART Mode) Clock Frequencies
        2. Table 4-15 eUSCI (UART Mode) Switching Characteristics
        3. Table 4-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 4-17 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 4-18 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 4-19 eUSCI (I2C Mode) Switching Characteristics
      9. 4.12.9  ADC
        1. Table 4-20 ADC, Power Supply and Input Range Conditions
        2. Table 4-21 ADC, Timing Parameters
        3. Table 4-22 ADC, Linearity Parameters
      10. 4.12.10 Enhanced Comparator (eCOMP)
        1. Table 4-23 eCOMP0
        2. Table 4-24 eCOMP1
      11. 4.12.11 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
        1. Table 4-25 SAC, OA
        2. Table 4-26 SAC, DAC
      12. 4.12.12 FRAM
        1. Table 4-27 FRAM
      13. 4.12.13 Emulation and Debug
        1. Table 4-28 JTAG, Spy-Bi-Wire Interface
        2. Table 4-29 JTAG, 4-Wire Interface
  5. 5Detailed Description
    1. 5.1  CPU
    2. 5.2  Operating Modes
    3. 5.3  Interrupt Vector Addresses
    4. 5.4  Memory Organization
    5. 5.5  Bootloader (BSL)
    6. 5.6  JTAG Standard Interface
    7. 5.7  Spy-Bi-Wire Interface (SBW)
    8. 5.8  FRAM
    9. 5.9  Memory Protection
    10. 5.10 Peripherals
      1. 5.10.1  Power Management Module (PMM) and On-Chip Reference Voltages
      2. 5.10.2  Clock System (CS) and Clock Distribution
      3. 5.10.3  General-Purpose Input/Output Port (I/O)
      4. 5.10.4  Watchdog Timer (WDT)
      5. 5.10.5  System Module (SYS)
      6. 5.10.6  Cyclic Redundancy Check (CRC)
      7. 5.10.7  Interrupt Compare Controller (ICC)
      8. 5.10.8  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_A1, eUSCI_B0, eUSCI_B1)
      9. 5.10.9  Timers (Timer0_B3, Timer1_B3, Timer2_B3, Timer3_B7)
      10. 5.10.10 Backup Memory (BKMEM)
      11. 5.10.11 Real-Time Clock (RTC) Counter
      12. 5.10.12 12-Bit Analog-to-Digital Converter (ADC)
      13. 5.10.13 Enhanced Comparator
      14. 5.10.14 Manchester Function Module (MFM)
      15. 5.10.15 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
      16. 5.10.16 eCOMP0, eCOMP1, SAC0, SAC1, SAC2, and SAC3 Interconnection (MSP430FR235x Devices Only)
      17. 5.10.17 Cross-Chip Interconnection (SACx are MSP430FR235x Devices Only)
      18. 5.10.18 Embedded Emulation Module (EEM)
      19. 5.10.19 Peripheral File Map
    11. 5.11 Input/Output Diagrams
      1. 5.11.1 Port P1 Input/Output With Schmitt Trigger
      2. 5.11.2 Port P2 Input/Output With Schmitt Trigger
      3. 5.11.3 Port P3 Input/Output With Schmitt Trigger
      4. 5.11.4 Port P4 Input/Output With Schmitt Trigger
      5. 5.11.5 Port P5 Input/Output With Schmitt Trigger
      6. 5.11.6 Port P6 Input/Output With Schmitt Trigger
    12. 5.12 Device Descriptors (TLV)
    13. 5.13 Identification
      1. 5.13.1 Revision Identification
      2. 5.13.2 Device Identification
      3. 5.13.3 JTAG Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Device Connection and Layout Fundamentals
      1. 6.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 6.1.2 External Oscillator
      3. 6.1.3 JTAG
      4. 6.1.4 Reset
      5. 6.1.5 Unused Pins
      6. 6.1.6 General Layout Recommendations
      7. 6.1.7 Do's and Don'ts
    2. 6.2 Peripheral- and Interface-Specific Design Information
      1. 6.2.1 ADC Peripheral
        1. 6.2.1.1 Partial Schematic
        2. 6.2.1.2 Design Requirements
        3. 6.2.1.3 Layout Guidelines
    3. 6.3 ROM Libraries
    4. 6.4 Typical Applications
  7. 7Device and Documentation Support
    1. 7.1 Getting Started
    2. 7.2 Device Nomenclature
    3. 7.3 Tools and Software
    4. 7.4 Documentation Support
    5. 7.5 Related Links
    6. 7.6 Trademarks
    7. 7.7 Electrostatic Discharge Caution
    8. 7.8 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Revision History

Changes from revision C to revision D

Changes from March 6, 2019 to December 10, 2019

  • Corrected the ROM size in Figure 1-1MSP430FR235x Functional Block Diagram and Figure 1-2MSP430FR215x Functional Block DiagramGo
  • Added a note on all VQFN pinouts to indicate that the thermal pad should be connected to VSSGo
  • Corrected Figure 3-4, 32-Pin RSM (VQFN) (Top View) – MSP430FR235xGo
  • Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in Section 4.3, Recommended Operating ConditionsGo
  • Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in Section 4.3, Recommended Operating ConditionsGo
  • Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 4.3, Recommended Operating ConditionsGo
  • Combined former sections 5.8 and 5.10 into Section 4.9, Production Distribution of LPM Supply CurrentsGo
  • Corrected the "SVS disabled" condition for Figure 4-1Go
  • Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" to Table 4-3, XT1 Crystal Oscillator (Low Frequency)Go
  • Changed the note that begins "Requires external capacitors at both terminals..." in Table 4-3, XT1 Crystal Oscillator (Low Frequency)Go
  • Corrected the test conditions for the RI parameter in Table 4-20, ADC, Power Supply and Input Range ConditionsGo
  • Removed ADCDIV from the equation for the ADC conversion time because ADCCLK is after division in Table 4-21, ADC, Timing ParametersGo
  • Added the note that begins "tSample = ln(2n+1) × τ ..." in Table 4-21, ADC, Timing ParametersGo
  • Changed the unit from "nV" to "µV" for the "Input noise voltage" in the Table 4-25, SAC, OAGo
  • Changed the unit from "nv/Hz" to "nV/√Hz" for the "Input noise voltage density" in the Table 4-25, SAC, OAGo
  • Changed the bitfield name from RTCCLK to RTCCKSEL in the table note on Table 5-9, Clock DistributionGo
  • Added Section 5.10.17, Cross-Chip Interconnection (SACx are MSP430FR235x Devices Only)Go
  • Added P1SELC information in Table 5-41, Port P1, P2 Registers (Base Address: 0200h)Go
  • Added P2SELC information in Table 5-41, Port P1, P2 Registers (Base Address: 0200h)Go
  • Added P3SELC information in Table 5-42, Port P3, P4 Registers (Base Address: 0220h)Go
  • Added P4SELC information in Table 5-42, Port P3, P4 Registers (Base Address: 0220h)Go
  • Added P5SELC information in Table 5-43, Port P5, P6 Registers (Base Address: 0240h)Go
  • Added P6SELC information in Table 5-43, Port P5, P6 Registers (Base Address: 0240h)Go
  • Changed CRC covered end address to 0x1AF7 in table note (1) in Table 5-70, Device DescriptorsGo

Changes from July 3, 2018 to March 5, 2019

  • Added 32-pin VQFN (RSM) package information in Section 1.1, FeaturesGo
  • Added 32-pin VQFN (RSM) package information to the Device Information table in Section 1.3, DescriptionGo
  • Added 32-pin VQFN (RSM) package information in Table 2-1, Device ComparisonGo
  • Added Figure 3-4, 32-Pin RSM (VQFN) (Top View) – MSP430FR235xGo
  • Added Figure 3-8, 32-Pin RSM (VQFN) (Top View) – MSP430FR215xGo
  • Added 32-pin VQFN (RSM) package information in Section 3.2, Pin AttributesGo
  • Added 32-pin VQFN (RSM) package information in Section 3.3, Signal DescriptionsGo
  • Added 32-pin VQFN (RSM) package information in Section 4.11, Thermal Resistance CharacteristicsGo

Changes from June 20, 2018 to July 2, 2018

Changes from May 11, 2018 to June 19, 2018

  • Changed the document status to PRODUCTION DATAGo
  • Added missing UCB0SCL signal to P1.3/UCB0SOMI/UCB0SCL/OA0+/A3 in pinout figuresGo
  • Added row for "Driver library and FFT library" in Table 5-4, Memory OrganizationGo
  • Added Section 6.3, ROM LibrariesGo
  • Corrected the title and link to reference design in Table 6-1, Tools and Reference DesignsGo