SLASEC4D May   2018  – December 2019 MSP430FR2153 , MSP430FR2155 , MSP430FR2353 , MSP430FR2355

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
      1.      Revision History
  2. 2Device Comparison
    1. 2.1 Related Products
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagrams
    2. 3.2 Pin Attributes
    3. 3.3 Signal Descriptions
    4. 3.4 Pin Multiplexing
    5. 3.5 Buffer Type
    6. 3.6 Connection of Unused Pins
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 4.5  Active Mode Supply Current Per MHz
    6. 4.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 4.7  Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 4.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 4.9  Production Distribution of LPM Supply Currents
    10. 4.10 Typical Characteristics - Current Consumption Per Module
    11. 4.11 Thermal Resistance Characteristics
    12. 4.12 Timing and Switching Characteristics
      1. 4.12.1  Power Supply Sequencing
        1. Table 4-1 PMM, SVS and BOR
      2. 4.12.2  Reset Timing
        1. Table 4-2 Wake-up Times From Low-Power Modes and Reset
      3. 4.12.3  Clock Specifications
        1. Table 4-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 4-4 XT1 Crystal Oscillator (High Frequency)
        3. Table 4-5 DCO FLL, Frequency
        4. Table 4-6 DCO Frequency
        5. Table 4-7 REFO
        6. Table 4-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        7. Table 4-9 Module Oscillator (MODOSC)
      4. 4.12.4  Internal Shared Reference
        1. Table 4-10 Internal Shared Reference
      5. 4.12.5  General-Purpose I/Os
        1. Table 4-11 Digital Inputs
        2. Table 4-12 Digital Outputs
      6. 4.12.6  Digital I/O Typical Characteristics
      7. 4.12.7  Timer_B
        1. Table 4-13 Timer_B
      8. 4.12.8  eUSCI
        1. Table 4-14 eUSCI (UART Mode) Clock Frequencies
        2. Table 4-15 eUSCI (UART Mode) Switching Characteristics
        3. Table 4-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 4-17 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 4-18 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 4-19 eUSCI (I2C Mode) Switching Characteristics
      9. 4.12.9  ADC
        1. Table 4-20 ADC, Power Supply and Input Range Conditions
        2. Table 4-21 ADC, Timing Parameters
        3. Table 4-22 ADC, Linearity Parameters
      10. 4.12.10 Enhanced Comparator (eCOMP)
        1. Table 4-23 eCOMP0
        2. Table 4-24 eCOMP1
      11. 4.12.11 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
        1. Table 4-25 SAC, OA
        2. Table 4-26 SAC, DAC
      12. 4.12.12 FRAM
        1. Table 4-27 FRAM
      13. 4.12.13 Emulation and Debug
        1. Table 4-28 JTAG, Spy-Bi-Wire Interface
        2. Table 4-29 JTAG, 4-Wire Interface
  5. 5Detailed Description
    1. 5.1  CPU
    2. 5.2  Operating Modes
    3. 5.3  Interrupt Vector Addresses
    4. 5.4  Memory Organization
    5. 5.5  Bootloader (BSL)
    6. 5.6  JTAG Standard Interface
    7. 5.7  Spy-Bi-Wire Interface (SBW)
    8. 5.8  FRAM
    9. 5.9  Memory Protection
    10. 5.10 Peripherals
      1. 5.10.1  Power Management Module (PMM) and On-Chip Reference Voltages
      2. 5.10.2  Clock System (CS) and Clock Distribution
      3. 5.10.3  General-Purpose Input/Output Port (I/O)
      4. 5.10.4  Watchdog Timer (WDT)
      5. 5.10.5  System Module (SYS)
      6. 5.10.6  Cyclic Redundancy Check (CRC)
      7. 5.10.7  Interrupt Compare Controller (ICC)
      8. 5.10.8  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_A1, eUSCI_B0, eUSCI_B1)
      9. 5.10.9  Timers (Timer0_B3, Timer1_B3, Timer2_B3, Timer3_B7)
      10. 5.10.10 Backup Memory (BKMEM)
      11. 5.10.11 Real-Time Clock (RTC) Counter
      12. 5.10.12 12-Bit Analog-to-Digital Converter (ADC)
      13. 5.10.13 Enhanced Comparator
      14. 5.10.14 Manchester Function Module (MFM)
      15. 5.10.15 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
      16. 5.10.16 eCOMP0, eCOMP1, SAC0, SAC1, SAC2, and SAC3 Interconnection (MSP430FR235x Devices Only)
      17. 5.10.17 Cross-Chip Interconnection (SACx are MSP430FR235x Devices Only)
      18. 5.10.18 Embedded Emulation Module (EEM)
      19. 5.10.19 Peripheral File Map
    11. 5.11 Input/Output Diagrams
      1. 5.11.1 Port P1 Input/Output With Schmitt Trigger
      2. 5.11.2 Port P2 Input/Output With Schmitt Trigger
      3. 5.11.3 Port P3 Input/Output With Schmitt Trigger
      4. 5.11.4 Port P4 Input/Output With Schmitt Trigger
      5. 5.11.5 Port P5 Input/Output With Schmitt Trigger
      6. 5.11.6 Port P6 Input/Output With Schmitt Trigger
    12. 5.12 Device Descriptors (TLV)
    13. 5.13 Identification
      1. 5.13.1 Revision Identification
      2. 5.13.2 Device Identification
      3. 5.13.3 JTAG Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Device Connection and Layout Fundamentals
      1. 6.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 6.1.2 External Oscillator
      3. 6.1.3 JTAG
      4. 6.1.4 Reset
      5. 6.1.5 Unused Pins
      6. 6.1.6 General Layout Recommendations
      7. 6.1.7 Do's and Don'ts
    2. 6.2 Peripheral- and Interface-Specific Design Information
      1. 6.2.1 ADC Peripheral
        1. 6.2.1.1 Partial Schematic
        2. 6.2.1.2 Design Requirements
        3. 6.2.1.3 Layout Guidelines
    3. 6.3 ROM Libraries
    4. 6.4 Typical Applications
  7. 7Device and Documentation Support
    1. 7.1 Getting Started
    2. 7.2 Device Nomenclature
    3. 7.3 Tools and Software
    4. 7.4 Documentation Support
    5. 7.5 Related Links
    6. 7.6 Trademarks
    7. 7.7 Electrostatic Discharge Caution
    8. 7.8 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Signal Descriptions

Table 3-2 describes the signals for all device variants and package options.

Table 3-2 Signal Descriptions

FUNCTION SIGNAL NAME PIN NUMBER(1) PIN TYPE(2) DESCRIPTION
PT RHA DBT RSM
ADC A0 3 2 7 2 I Analog input A0
A1 2 1 6 1 I Analog input A1
A2 1 40 5 32 I Analog input A2
A3 48 39 4 31 I Analog input A3
A4 34 28 31 22 I Analog input A4
A5 33 27 30 21 I Analog input A5
A6 32 26 29 20 I Analog input A6
A7 31 25 28 19 I Analog input A7
A8 43 34 37 I Analog input A8
A9 42 33 36 I Analog input A9
A10 41 I Analog input A10
A11 40 I Analog input A11
Veref+ 3 2 7 2 I ADC positive reference
Veref- 1 40 5 32 I ADC negative reference
eCOMP0 C0 3 2 7 2 I Comparator input channel C0
C1 2 1 6 1 I Comparator input channel C1
COUT 30 24 27 18 O Comparator output channel COUT
eCOMP1 C0 10 9 14 9 I Comparator input channel C0
C1 11 10 15 10 I Comparator input channel C1
COUT 29 23 26 17 O Comparator output channel COUT
SAC0(4) OA0+ 48 39 4 31 I SAC0, OA positive input
OA0- 1 40 5 32 I SAC0, OA negative input
OA0O 2 1 6 1 O SAC0, OA output
SAC1(4) OA1+ 31 25 28 19 I SAC1, OA positive input
OA1- 32 26 29 20 I SAC1, OA negative input
OA1O 33 27 30 21 O SAC1, OA output
SAC2(4) OA2+ 44 35 38 27 I SAC2, OA positive input
OA2- 45 36 1 28 I SAC2, OA negative input
OA2O 46 37 2 29 O SAC2, OA output
SAC3(4) OA3+ 35 29 32 23 I SAC3, OA positive input
OA3- 36 30 33 24 I SAC3, OA negative input
OAO 37 31 34 25 O SAC3, OA output
Clock ACLK 2 1 6 1 O ACLK output
MCLK 9 8 13 8 O MCLK output
47 38 3 30 O
SMCLK 3 2 7 2 O SMCLK output
38 32 35 26 O
XIN 8 7 12 7 I Input terminal for crystal oscillator
XOUT 9 8 13 8 O Output terminal for crystal oscillator
Debug SBWTCK 4 3 8 3 I Spy-Bi-Wire input clock
SBWTDIO 5 4 9 4 I/O Spy-Bi-Wire data input/output
TCK 34 28 31 22 I Test clock
TCLK 32 26 29 20 I Test clock input
TDI 32 26 29 20 I Test data input
TDO 31 25 28 19 O Test data output
TMS 33 27 30 21 I Test mode select
TEST 4 3 8 3 I Test mode pin – selected digital I/O on JTAG pins
System NMI 5 4 9 4 I Nonmaskable interrupt input
RST 5 4 9 4 I/O Reset input, active-low
Power DVCC 6 5 10 5 P Power supply
DVSS 7 6 11 6 P Power ground
VREF+ 31 25 28 19 P Output of positive reference voltage with ground as reference
GPIO, Port 1 P1.0 3 2 7 2 I/O General-purpose I/O
P1.1 2 1 6 1 I/O General-purpose I/O
P1.2 1 40 5 32 I/O General-purpose I/O
P1.3 48 39 4 31 I/O General-purpose I/O
P1.4 34 28 31 22 I/O General-purpose I/O (3)
P1.5 33 27 30 21 I/O General-purpose I/O (3)
P1.6 32 26 29 20 I/O General-purpose I/O(3)
P1.7 31 25 28 19 I/O General-purpose I/O(3)
GPIO, Port 2 P2.0 30 24 27 18 I/O General-purpose I/O
P2.1 29 23 26 17 I/O General-purpose I/O
P2.2 28 22 25 I/O General-purpose I/O
P2.3 27 21 24 I/O General-purpose I/O
P2.4 11 10 15 10 I/O General-purpose I/O
P2.5 10 9 14 9 I/O General-purpose I/O
P2.6 9 8 13 8 I/O General-purpose I/O
P2.7 8 7 12 7 I/O General-purpose I/O
GPIO, Port 3 P3.0 47 38 3 30 I/O General-purpose I/O
P3.1 46 37 2 29 I/O General-purpose I/O
P3.2 45 36 1 28 I/O General-purpose I/O
P3.3 44 35 38 27 I/O General-purpose I/O
P3.4 38 32 35 26 I/O General-purpose I/O
P3.5 37 31 34 25 I/O General-purpose I/O
P3.6 36 30 33 24 I/O General-purpose I/O
P3.7 35 29 32 23 I/O General-purpose I/O
GPIO, Port 4 P4.0 26 20 23 16 I/O General-purpose I/O
P4.1 25 19 22 15 I/O General-purpose I/O
P4.2 24 18 21 14 I/O General-purpose I/O
P4.3 23 17 20 13 I/O General-purpose I/O
P4.4 15 14 19 I/O General-purpose I/O
P4.5 14 13 18 I/O General-purpose I/O
P4.6 13 12 17 12 I/O General-purpose I/O
P4.7 12 11 16 11 I/O General-purpose I/O
GPIO, Port 5 P5.0 43 34 37 I/O General-purpose I/O
P5.1 42 33 36 I/O General-purpose I/O
P5.2 41 I/O General-purpose I/O
P5.3 40 I/O General-purpose I/O
P5.4 39 I/O General-purpose I/O
GPIO, Port 6 P6.0 22 16 I/O General-purpose I/O
P6.1 21 15 I/O General-purpose I/O
P6.2 20 I/O General-purpose I/O
P6.3 19 I/O General-purpose I/O
P6.4 18 I/O General-purpose I/O
P6.5 17 I/O General-purpose I/O
P6.6 16 I/O General-purpose I/O
UART UCA0TXD 31 25 28 19 O eUSCI_A0 UART transmit data
UCA0RXD 32 26 29 20 I eUSCI_A0 UART receive data
UCA1TXD 23 17 20 13 O eUSCI_A1 UART transmit data
UCA1RXD 24 18 21 14 I eUSCI_A1 UART receive data
ISO ISOTXD 26 20 23 16 O ISO transmit data (the logical AND product of UCA1TXD and TB3.2B)
ISORXD 26 20 23 16 I ISO receive data (to UCA1RXD and TB3.CCI2B)
SPI UCA0STE 34 28 31 22 I/O eUSCI_A0 SPI slave transmit enable
UCA0CLK 33 27 30 21 I/O eUSCI_A0 SPI clock input/output
UCA0SOMI 32 26 29 20 I/O eUSCI_A0 SPI slave out/master in
UCA0SIMO 31 25 28 19 I/O eUSCI_A0 SPI slave in/master out
UCA1STE 26 20 23 16 I/O eUSCI_A1 SPI slave transmit enable
UCA1CLK 25 19 22 15 I/O eUSCI_A1 SPI clock input/output
UCA1SOMI 24 18 21 14 I/O eUSCI_A1 SPI slave out/master in
UCA1SIMO 23 17 20 13 I/O eUSCI_A1 SPI slave in/master out
UCB0STE 3 2 7 2 I/O eUSCI_B0 slave transmit enable
UCB0CLK 2 1 6 1 I/O eUSCI_B0 clock input/output
UCB0SIMO 1 40 5 32 I/O eUSCI_B0 SPI slave in/master out
UCB0SOMI 48 39 4 31 I/O eUSCI_B0 SPI slave out/master in
UCB1STE 15 14 19 I/O eUSCI_B1 slave transmit enable
UCB1CLK 14 13 18 I/O eUSCI_B1 clock input/output
UCB1SIMO 13 12 17 I/O eUSCI_B1 SPI slave in/master out
UCB1SOMI 12 11 16 I/O eUSCI_B1 SPI slave out/master in
I2C UCB0SCL 48 39 4 31 I/O eUSCI_B0 I2C clock
UCB0SDA 1 40 5 32 I/O eUSCI_B0 I2C data
UCB1SCL 12 11 16 11 I/O eUSCI_B1 I2C clock
UCB1SDA 13 12 17 12 I/O eUSCI_B1 I2C data
Timer_B TB0.1 32 26 29 20 I/O Timer TB0 CCR1
capture: CCI1A input, compare: Out1 output
TB0.2 31 25 28 19 I/O Timer TB0 CCR2
capture: CCI2A input
compare: Out2 output
TB0TRG 1 40 5 32 I TB0 external trigger input for TB0OUTH
TB0CLK 8 7 12 7 I Timer clock input TBCLK for TB0
TB1.1 30 24 27 18 I/O Timer TB1 CCR1
capture: CCI1A input
compare: Out1 output
TB1.2 29 23 26 17 I/O Timer TB1 CCR2
capture: CCI2A input
compare: Out2 output
TB1CLK 28 22 25 I Timer clock input TBCLK for TB1
TB1TRG 27 21 24 I TB1 external trigger input for TB1OUTH
TB2.1 43 34 37 I/O Timer TB2 CCR1
capture: CCI1A input
compare: Out1 output
TB2.2 42 33 36 I/O Timer TB2 CCR2
capture: CCI2A input
compare: Out2 output
TB2CLK 41 I Timer clock input TBCLK for TB2
TB2TRG 40 I TB2 external trigger input for TB2OUTH
TB3.1 22 16 I/O Timer TB3 CCR1
capture: CCI1A input
compare: Out1 output
TB3.2 21 15 I/O Timer TB3 CCR2
capture: CCI2A input
compare: Out2 output
TB3.3 20 I/O Timer TB3 CCR3
capture: CCI3A input
compare: Out3 output
TB3.4 19 I/O Timer TB3 CCR4
capture: CCI4A input
compare: Out4 output
TB3.5 18 I/O Timer TB3 CCR5
capture: CCI5A input
compare: Out5 outputs
TB3.6 17 I/O Timer TB3 CCR6
capture: CCI6A input
compare: Out6 output
TB3CLK 16 I Timer clock input TBCLK for TB3
MFM TX 42 33 36 O Manchester function module transmit
RX 43 34 37 I Manchester function module receive
VQFN thermal pad Pad Pad Connect the exposed thermal pad to VSS.
Any pin that is not bonded out in a smaller package must be initialized by software after reset to achieve the lowest leakage current.
I = input, O = output, I/O = input/output, P = power
Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to prevent collisions.
Functions shared with these four pins cannot be debugged if 4-wire JTAG is used for debug.
MSP430FR235x devices only